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| AP7217_10 Datasheet, PDF (4/10 Pages) Diodes Incorporated – 500mA CMOS LDO | |||
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AP7217
500mA CMOS LDO
Electrical Characteristics (VIN = 12V, TA = +25°C, unless otherwise noted)
(TA = 25°C, CIN = 1µF, COUT = 1µF, VEN = VIN, unless otherwise noted)
Symbol
Parameter
Test Conditions
Min Typ. Max Unit
IQ
Quiescent Current
IO = 0mA
ISTB
Standby Current
VEN = Off
VIN = 5.0V
-
50 70 μA
15 30
μA
VROUT
Output Voltage Accuracy IO = 30mA, VIN = 5V
VROUT Temperature
Coefficient
-40°C to 85°C, IOUT = 30mA
3.234 3.300 3.366 V
±100
ppm /
oC
VDROPOUT
Dropout Voltage
IOUT = 100mA
100 250 mV
Maximum Output
IOUT
Current
VIN = 5.3V
500
mA
ILIMIT
Current Limit
VIN = 5.3V
600
mA
Ishort
Short Circuit Current VIN = 5.3V
50
mA
ÎVLINE/ÎVIN/VROUT Line Regulation
4.3V ⤠VIN ⤠5.5V; IOUT = 30mA
0.01 ±0.2 %/V
ÎVROUT
Load Regulation
1mA ⤠IOUT ⤠100mA, VIN = 5.3V
15 50 mV
VIN = 4.3V+ 0.5Vp-
PSRR
Power Supply Rejection pAC,
F= 1KHz
55
dB
IOUT = 50mA
VEH
Output ON
EN Input Threshold
VEL
Output OFF
1.6
V
0.25 V
IEN
Enable Pin Current
-0.1
0.1 μA
VDF
Detect fall voltage
3.83 3.91 3.98 V
VHysteresis
VD Hysteresis Range
VDF
VDF
VDF
V
x1.02 x1.05 x1.08
IVDOUT
VD Supply Current
VDOUT = 0.5V
VIN = 2.0V
3.0V
mA
20
30
tRP
VDOUT Delay Time
VIN = 1.8V to VDF+ 1V
Thermal Resistance
θJA
Junction to Ambient
SOP-8L (Note 2)
10 20 40 mSec
134
ºC/W
Thermal Resistance
θJC
SOP-8L (Note 2)
Junction to Case
28
ºC/W
Notes: 2. Test conditions for SOP-8L: Devices mounted on FR-4 PC board, MRP, 2oz copper layout, calibrate at TJ=150 ºC, measure at
TA=25ºC, minimum recommended pad layout
AP7217
Document number: DS31292 Rev. 4 - 2
4 of 10
www.diodes.com
April 2010
© Diodes Incorporated
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