DA7211 Datasheet, PDF (89/105 Pages) Dialog Semiconductor – Ultra-low power stereo codec

DA7211
Ultra-low power stereo codec
Company confidential
Table 79: PLL 0x2C
Bit
Mode
Symbol
7
R/W
PLL_EN
6
R/W
MCLK_SRM_EN
5
R/W
MCLK_DET_EN
4
R/W
MCLK_SHAPE_EN
Description
PLL enable
0 = disable and bypass PLL
1 = enable PLL
Sample rate tracking
0 = disabled
1 = enabled
automatic detection of sample rate
0 = disabled
1 = enabled
Enable MCLK shaper for low level non TTL signals
0 = disabled
1 = enabled
In MCLK_DET mode, the value read from this
register will be the automatically detected sample
rate from the PLL track circuitry. This will be
updated on the positive edge of the DAI clock.
Reset
0
0
0
0
3:0
R/W
FS
0000 = reserved
0001 = 8 kHz
0010 = 11.025 kHz
0011 = 12 kHz
0100 = reserved
0101 = 16 kHz
0110 = 22.05 kHz
0111 = 24 kHz
1000= reserved
1001 = 32 kHz
1010 = 44.1 kHz
1011 = 48 kHz
1100 = reserved
1101 = reserved
1110 = 88.2 kHz
1111 = 96 kHz
1010
10.4 GP filter engine
Table 80: GP1A A0L 0x2D
Bit
Mode
Symbol
7:0
W
GP1A A0L
Table 81: GP1A A0H 0x2E
Bit
Mode
Symbol
7:0
W
GP1A A0H
Description
A0L bit 7:0 of A0 coefficient
Description
A0H bit 15:8 of A0 coefficient
Reset
00000000
Reset
01000000
Datasheet
CFR0011-120-00 Rev 5
Revision 3e
89 of 105
15-Oct-2015
© 2015 Dialog Semiconductor