DA7211 Datasheet, PDF (65/105 Pages) Dialog Semiconductor – Ultra-low power stereo codec

DA7211
Ultra-low power stereo codec
Company confidential
10 Register definitions
WARNING: Any writes to RESERVED registers or bits can result in unexpected operation. This
section gives an overview of all user accessible registers in the Register map table.
Detailed descriptions are given in Register description tables, which are grouped per functional block.
10.1 Register map
Table 38: Register map
A d d ress
1
2
3
4
5
7
8
9
0a
0c
0d
0e
0f
10
11
12
13
14
15
16
17
18
19
1a
1b
1c
1d
1e
1f
21
22
23
24
25
26
27
28
29
2a
2b
2c
2d
2e
2f
30
31
F unct io n
7
6
5
4
3
2
1
0
D ef ault
CONTROL WRITE_M ODE
NOISE_ SUP
B IA S_ EN
V _ IO
0 b 0 0 0 10 0 0 0
STA TUS
M UTING
SOFTM UTED
I2 S_ LOCK
PLL_ LOCK
0b00000000
STARTUP1 SC_CLK_DIS
SC_ OV ERRIDE
SC_M ST_EN 0b00000000
STA RTUP2
STARTUP2[ 6:0]
0b00000000
STA RTUP3
STARTUP3[ 6:0]
0b00000000
M IC_L
M IC_L_EN M ICBIAS_EN
M ICBIAS_SEL[ 1:0]
M IC_L_M UTE
M IC_L_VOL[ 2:0]
0b00000000
M IC_R
M IC_R_EN
M IC_R_M UTE
M IC_R_VOL[ 2:0]
0b00000000
A UX 1_ L
A UX 1_ L_ EN
AUX1_L_VOL[ 5:0]
0 b 0 0 0 10 0 0 0
A UX 1_ R
A UX 1_ R_ EN
AUX1_R_VOL[ 5:0]
0 b 0 0 0 10 0 0 0
IN_ GA IN
INPGA_R_VOL[ 3:0]
INPGA_L_VOL[ 3:0]
0b00000000
INM IX_L
IN_ L_ EN
IN_L_OUTM IX_L
IN_ L_ A 1_ L
IN_L_M IC_R IN_L_M IC_L 0b00000000
INM IX_R
IN_ R_ EN
IN_R_IN_L IN_R_OUTM IX_R
IN_R_A1_R IN_L_M IC_L IN_L_M IC_R 0b00000000
ADC_HPF ADC_VOICE_EN
ADC_VOICE_F0[ 2:0]
A DC_ HPF_ EN
ADC_HPF_F0[ 1:0]
0 b 0 0 0 0 10 0 0
ADC
ADC_R_EN ADC_R_M UTE
ADC_L_EN ADC_L_M UTE
A LC_ EN
0b00000000
A DC_ EQ1_ 2
ADC_EQ2_VOL[ 7:4]
ADC_EQ1_VOL[ 3:0]
0b00000000
A DC_ EQ3 _ 4
ADC_EQ4_VOL[ 7:4]
ADC_EQ3_VOL[ 3:0]
0b00000000
A DC_ EQ5
A DC_ EQ_ EN
ADC_EQ_GAIN[ 1:0]
ADC_EQ5_VOL[ 3:0]
0b00000000
DAC_HPF DAC_VOICE_EN
DAC_VOICE_F0[ 2:0]
DAC_HPF_EN DAC_M UTE
DAC_HPF_F0[ 1:0]
0 b 0 0 0 0 10 0 0
DAC_L
DA C_ L_ INV
DAC_L_GAIN[ 6:0]
0 b 0 0 0 10 0 0 0
DAC_R
DA C_ R_ INV
DAC_R_GAIN[ 6:0]
0 b 0 0 0 10 0 0 0
DA C_ SEL
DA C_ R_ EN
DAC_R_SRC[ 2:0]
DA C_ L_ EN
DAC_L_SRC[ 2:0]
0 b 0 10 10 10 0
SOFT_M UTE SOFT_M UTE RAM P_EN
M UTE_RATE[ 2:0]
0 b 0 10 0 0 0 0 0
DA C_ EQ1_ 2
DAC_EQ2_VOL[ 7:4]
DAC_EQ1_VOL[ 3:0]
0b00000000
DA C_ EQ3 _ 4
DAC_EQ4_VOL[ 7:4]
DAC_EQ3_VOL[ 3:0]
0b00000000
DA C_ EQ5
DA C_ EQ_ EN
DA C_ EQ_ GA IN
DAC_EQ5_VOL[ 3:0]
0b00000000
OUTM IX_L
OUT_ L_ EN
OUT_ L_ INV
OUT_L_DAC_L OUT_L_IN_R OUT_L_IN_L
OUT_L_A1_L 0b00000000
OUTM IX_R
OUT_ R_ EN
OUT_ R_ INV
OUT_R_DAC_R OUT_R_IN_R OUT_R_IN_L
OUT_R_A1_R 0b00000000
OUT1_ L
OUT1_ L_ EN
OUT1_ L_ SE
OUT1_L_VOL[ 5:0]
0 b 0 0 110 10 1
OUT1_ R
OUT1_R_EN OUT1_R_SE
OUT1_R_VOL[ 5:0]
0 b 0 0 110 10 1
HP_ L_ V OL
HP_L_VOL[ 5:0]
0 b 0 0 0 10 0 0 0
HP_ R_ V OL
HP_R_VOL[ 5:0]
0 b 0 0 0 10 0 0 0
HP_ CFG
HP_ R_ EN
HP_M ODE STEREO_TRACK HP_HIGHZ_R
HP_ L_ EN
HP_2CAP_M ODE HP_HIGHZ_L 0b00000010
ZEROX
HPZX_R_EN HPZX_L_EN OUTZX_R_EN OUTZX_L_EN INZX_R_EN
INZX _ L_ EN
A 1ZX _ R_ EN
A1ZX_L_EN 0b00000000
DAI_SRC_SEL DAI_IN_R_M IX
DAI_OUT_R_SRC[ 2:0]
DAI_IN_L_M IX
DAI_OUT_L_SRC[ 2:0]
0 b 0 1110 110
DA I_ CFG1
DAI_M ODE
DAI_TDM _M ONO
DAI_FRAM E[ 1:0]
DAI_WORD[ 1:0]
0b00000000
DA I_ CFG2
DAI_TDM _OFFS[ 7:0]
0b00000000
DA I_ CFG3
DA I_ EN
DA I_ OE
DA I_ TDM
DAI_FORM AT[ 1:0]
0 b 0 0 0 0 10 0 0
PLL_ DIV 1
PLL_DIV_H[ 7:0]
0b00000000
PLL_ DIV 2
PLL_DIV_M [ 7:0]
0b00000000
PLL_ DIV 3
PLL_ B Y P
M CLK_RANGE[ 1:0]
PLL_DIV_L[ 3:0]
0 b 0 0 0 10 0 0 0
PLL
PLL_EN M CLK_SRM _EN M CLK_DET_ENM CLK_SHAPE_EN
FS[ 3:0]
0 b 0 0 0 0 10 10
GP1A _ A 0 L
GP1A_A0L[ 7:0]
0b00000000
GP1A _ A 0 H
GP1A_A0H[ 7:0]
0 b 0 10 0 0 0 0 0
GP1B _ A 0 L
GP1B_A0L[ 7:0]
0b00000000
GP1B _ A 0 H
GP1B_A0H[ 7:0]
0 b 0 10 0 0 0 0 0
GP2 A _ A 0 L
GP2A_A0L[ 7:0]
0b00000000
Datasheet
CFR0011-120-00 Rev 5
Revision 3e
65 of 105
15-Oct-2015
© 2015 Dialog Semiconductor