DA14583 Datasheet, PDF (73/148 Pages) Dialog Semiconductor – Low Power Bluetooth Smart SoC with Flash memory

Table 108: UART2_LSR_REG (0x50001114)
Bit
Mode Symbol
1
R
UART_OE
0
R
UART_DR
Description
Overrun error bit.
This is used to indicate the occurrence of an overrun error.
This occurs if a new data character was received before the
previous data was read.
In the non-FIFO mode, the OE bit is set when a new character
arrives in the receiver before the previous character was read
from the RBR. When this happens, the data in the RBR is
overwritten. In the FIFO mode, an overrun error occurs when
the FIFO is full and a new character arrives at the receiver.
The data in the FIFO is retained and the data in the receive
shift register is lost.
0 = no overrun error
1 = overrun error
Reading the LSR clears the OE bit.
Data Ready bit.
This is used to indicate that the receiver contains at least one
character in the RBR or the receiver FIFO.
0 = no data ready
1 = data ready
This bit is cleared when the RBR is read in non-FIFO mode,
or when the receiver FIFO is empty, in FIFO mode.
Reset
0x0
0x0
Table 109: UART2_MSR_REG (0x50001118)
Bit
Mode Symbol
15:8 -
-
7
R
UART_DCD
6
R
UART_R1
5
-
-
Description
Reserved
Data Carrier Detect.
This is used to indicate the current state of the modem control
line dcd_n. This bit is the complement of dcd_n. When the
Data Carrier Detect input (dcd_n) is asserted it is an indica-
tion that the carrier has been detected by the modem or data
set.
0 = dcd_n input is de-asserted (logic 1)
1 = dcd_n input is asserted (logic 0)
In Loopback Mode (MCR[4] set to one), DCD is the same as
MCR[3] (Out2).
Ring Indicator.
This is used to indicate the current state of the modem control
line ri_n. This bit is the complement of ri_n. When the Ring
Indicator input (ri_n) is asserted it is an indication that a tele-
phone ringing signal has been received by the modem or data
set.
0 = ri_n input is de-asserted (logic 1)
1 = ri_n input is asserted (logic 0)
In Loopback Mode (MCR[4] set to one), RI is the same as
MCR[2] (Out1).
Reserved
Reset
0x0
0x0
0x0
0x0
© 2014 Dialog Semiconductor
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Target - March 06, 2015 v1.1