DA7210 Datasheet, PDF (66/113 Pages) Dialog Semiconductor – Ultra-low power stereo codec

DA7210
Ultra-low power stereo codec
Table 40: 4 wire clock configurations
Parameter
nCS
Signal lines
SI Serial input data
SO Serial output data
SK
Interface
Push-pull with tristate
Data rate
Effective read/write
data
Transmission
Half-duplex
16 bit cycles
CPOL
Configuration
CPHA
RW-POL
nCS- POL
Company confidential
Chip select
Master out Slave in
Master in Slave out
Transmission clock
Up to 7 Mbps
MSB first
7-bit address, 1-bit read/write, 8-bit data
clock polarity (default 0 = clock idles low)
clock phase (default 1 = register data at falling edge)
R/W bit level for reading (default 1 = high level for reading)
active level of nCS (default 0 = active low)
nCS
SK
SI
SO
4-WIRE WRITE
A6
A5
A4
A3
A2
A1
A0 R/Wn D7
D6
D5
D4
D3
D2
D1
D0
4-WIRE READ
nCS
SK
SI
A6
A5
A4
A3
A2
A1
A0 R/Wn
SO
HI-Z
latch data
D7
D6
D5
D4
D3
D2
D1
D0
Figure 45: 4-wire host write and read timing (nCS_POL = ‘0’, CPOL = ‘0’, CPHA = ‘1’’)
Note 13 Accessing a register at high clock rates directly after writing it does not guarantee a correct value. It is
recommended to keep a delay of one frame until re-accessing a register that has just been written (for
example by writing/reading another register address in between).
9.2.8 2-wire communication
The 2-wire interface supports 7-bit address protocol. DA7210 responds to the device address
001 1010.
SK provides the 2-wire clock and SI carries all the control bidirectional 2-wire data. The 2-wire
interface is open-drain, supporting multiple devices on a single line. The attached devices only drive
the bus lines low by connecting them to ground.
Datasheet
CFR0011-120-00 Rev 5
Revision 3a
66 of 113
15-Oct-2015
© 2015 Dialog Semiconductor