DA7210 Datasheet, PDF (23/113 Pages) Dialog Semiconductor – Ultra-low power stereo codec

DA7210
Ultra-low power stereo codec
Company confidential
7 Timing characteristics
7.1 Digital audio interface timing - I2S/DSP (in master/slave mode)
WCLK
CLK
DATOUT
DATIN
T
tdCW
tf
tdWD
tsW
tr
tsD
thW
thC
thD
tlC
tdCD
Figure 4: I2S/DSP timing diagram
Table 16: I2S/DSP timing characteristics
(Ta = -40 to +85ºC)
Parameter Description
Input impedance
Conditions
DC impedance > 10 MΩ
T
tr
tf
thC
tlC
tdCW
tdCD
thW
tlW
tsW
thW
tsD
thD
t_dWD
CLK period
CLK rise time
CLK fall time
CLK high period
CLK low period
CLK to WCLK delay
CLK to DATOUT delay
WCLK high time
DSP mode
Non-DSP mode
WCLK low time
DSP mode
Non-DSP mode
WCLK setup time
WCLK hold time
DATIN setup time
DATIN hold time
DATOUT to WCLK delay
Slave mode
Slave mode
Min
Typ
Max Unit
300
Ω
1.0
2.5
pF
75
ns
8
ns
8
ns
40%
60%
T
40%
60%
T
-30%
+30%
T
-30%
+30%
T
100%
T
Word
T
length
100%
T
Word
T
length
7
ns
2
ns
7
ns
2
ns
DATOUT is synchronised to CLK
Datasheet
CFR0011-120-00 Rev 5
Revision 3a
23 of 113
15-Oct-2015
© 2015 Dialog Semiconductor