DA9062 Datasheet, PDF (58/93 Pages) Dialog Semiconductor – Entry level PMIC for applications requiring up to 8.5 A

DA9062
Entry level PMIC for applications requiring up to 8.5 A
9.2.1 General recommendations
Appropriate trace width and quantity of vias should be used for all power supply paths.
Too high trace resistances can prevent the system from achieving the best performance, for
example, the efficiency and the current ratings of switching converters might be degraded.
Furthermore, the PCB may be exposed to thermal hot spots, which can lead to critical overheating
due to the positive temperature coefficient of copper.
Special care must be taken with the DA9062 pad connections. The traces connecting the pads
should of the same width as the pads and they should become wider as soon as possible.
It is recommended to create a separate quiet ground to which the VREF capacitor, IREF resistor, and
the crystal capacitors are connected. The PCB layout should ensure these component grounds are
kept quiet, that is, they should be separated from the main ground return path for the noisy power
ground. The quiet ground can then be connected to the main ground at the paddle, as shown in
Figure 23.
All traces carrying high discontinuous currents should be kept as short as possible.
Noise sensitive analog signals, such as feedback lines or crystal connections, should be kept away
from traces carrying pulsed analog or digital signals. This can be achieved by separation or shielding
with quiet signals or ground traces.
9.2.2 LDOs and switched mode supplies
The placement of the distributed capacitors on the VSYS rail must ensure that all VDD inputs and
VSYS are connected to a bypass capacitor close to the pad. It is recommended placing at least two
1 µF capacitors close to the VDD_LDOx pads and at least one 10 µF close to the VDD_BUCKx pads.
Using a local power plane underneath the device for VSYS might be considered.
Transient current loops in the area of the switching converters should be minimised.
The common references (IREF, VREF) should be placed close to the device and cross-coupling to
any noisy digital or analog trace must be avoided.
Output capacitors of the LDOs can be placed close to the input pins of the supplied devices (remote
from the DA9062).
Care must be taken with trace routing to ensure that no current is carried on feedback lines of the
buck output voltages (VBUCKx).
The inductor placement is less critical since parasitic inductances have negligible effect.
9.2.3 32 kHz crystal oscillator
The crystal and its load capacitors should be placed as close as possible to the IC with short and
symmetrical traces.
The traces must be isolated from noisy signals, especially from clocked digital ones. Ideally the lines
should be buried between two ground layers, surrounded by additional ground traces.
9.2.4 Optimising thermal performance
DA9062 features a ground paddle which should be connected with as many vias as possible to the
PCB’s main ground plane in order to achieve good thermal performance.
Solder mask openings for the ball landing pads must be arranged to prohibit solder balls flowing into
vias.
Datasheet
Revision 3.2
58 of 93
18-Feb-2015
© 2016 Dialog Semiconductor