DA7212 Datasheet, PDF (47/129 Pages) Dialog Semiconductor – Ultra-low power stereo codec

DA7212
Ultra-low power stereo codec
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13.25 Clock modes
The DA7212 requires a clock for operation of various circuits within the chip. There are four ways in
which the main system clock may be generated:
● PLL bypass mode: If digital playback or record is required, the MCLK frequency should be set to
one of 11.2896/12.288 MHz or 22.5792/24.576 MHz or 45.1584/49.152 MHz (Note 17). The
PLL_INDIV register bit must then be programmed accordingly
● Normal PLL mode: Alternative frequency clock applied to MCLK pin (in the range of 2 to 50
MHz), where MCLK is synchronous with WCLK, or Master Mode is enabled
● SRM PLL mode: Clock applied to MCLK pin (in the range of 2 to 50 MHz) is asynchronous to
WCLK
● 32 kHz mode: Watch crystal frequency (32.768 kHz) clock applied to MCLK
Table 33: PLL clock modes
Mode
PLL bypassed
PLL enabled
PLL enabled SRM
enabled
PLL enabled 32 kHz
enabled
Master
Yes (Note 17)
Yes (Note 18)
No
Yes (Note 19)
Slave
Yes (Note 20)
Yes (Note 21)
Yes (Note 22)
No
Note 17 11.2896 MHz (or multiples) should be used as MCLK frequency for 11.025, 22.05, 44.1, 88.2 kHz
sample rates and 12.288 MHz (or multiples) should be used for 8, 12, 16, 24, 32, 48, 96 kHz sample
rates
Note 18 MCLK must be between 2 MHz and 50 MHz
Note 19 MCLK must be 32.768 kHz
Note 20 MCLK must be exactly 12.288 MHz or 11.2896 MHz or a multiple thereof and synchronous with BCLK
and WCLK
Note 21 MCLK must be synchronous with BCLK and WCLK
Note 22 BCLK must be synchronous with WCLK. MCLK must be between 2 MHz and 50 MHz
With the default register settings, the clock input should be a square wave with CMOS logic levels
(referenced to VDD_IO). A ‘clock squarer circuit’ can be enabled by asserting the
PLL_MCLK_SQR_EN register bit. This clock squarer allows a sine wave or other a low amplitude
clock (down to 300 mVpp) to be applied to the codec. The input is AC coupled on chip when using
the clock squarer mode. If the MCLK input frequency drops below 1 MHz, the PLL_MCLK_STATUS
bit is cleared, and the chip will automatically use its internal reference oscillator as a clock source.
Datasheet
Revision 3c
47 of 129
24-Nov-2015
© 2015 Dialog Semiconductor