DA9061 Datasheet, PDF (30/82 Pages) Dialog Semiconductor – Entry level PMIC for applications requiring up to 6 A

DA9061
Entry level PMIC for applications requiring up to 6 A
A repeated write mode can be enabled with WRITE_MODE control. In this mode, the master can
execute back-to-back write operations to non-consecutive addresses by transmitting register
addresses and data pairs. The data is stored in the address specified by the preceding byte. The
repeated write mode is illustrated in Figure 13.
S SLAVEadr W A REGadr A
7-bits 1 bit
8-bits
DATA
A
8-bits 1-bit
REGadr
8-bits
A DATA A ………. A P
8-bits
Repeated writes
Master to Slave
Slave to Master
S = START condition
Sr = Repeat START condition
P = STOP condition
A = Acknowledge (low)
A^* = No Acknowledge
W = Write (low)
R = Read (high)
Figure 13: 2-wire repeated write
If a new START or STOP condition occurs within a message, the bus returns to idle mode.
6.3 GPIOs
DA9061 features five general purpose IO pins. The basic structure of the GPIOs is depicted in
Figure 14. As illustrated, there are several additional functions:
● analog function
● alternate function
● forwarding
● regulator control
● sequencer WAIT_STEP
● interrupt and wakeup generation
The GPIOs are operational in POWERDOWN and ACTIVE modes. However, GPIs can be
configured as disabled in POWERDOWN mode in register PD_DIS (control GPI_DIS). In other
modes, the GPIO is disabled and all ports are configured as open drain outputs in high impedance
state. The level transitions on inputs will no longer be detected, but I/O drivers will keep their
configuration and programmed levels.
Analog function
Alternate
function
Forwarding
output
Sequencer (WAIT_STEP),
regulator control
Interrupt
GPIOx_MODE
GPIOx_PIN
Debounce
GPIOx_TYPE
M_GPIOx
GPIOx_WKUP_MODE
GPI
GPIOx_PUPD
GPIx
GPIOx_PIN
Edge
detection
E_GPIOx
Mask
Wakeup
selection
Wakeup
enable
VDDIO
GPIOx_PUPD
GPO OD
GPO push-pull
VDDIO
GPIOx_MODE
0
1
GPIOx_OUT
Output
function
GPIOx_WEN
Wakeup
Forwarding input
Sequencer
VDD_FAULT
Figure 14: General GPIO block diagram
The functionality of a GPIO is configured in GPIO<x>_PIN, as listed in Table 19.
Datasheet
CFR0011-120-00 Rev 5
Revision 3.2
30 of 82
01-Mar-2016
© 2016 Dialog Semiconductor