DA14582_16 Datasheet, PDF (12/172 Pages) Dialog Semiconductor – Bluetooth Low Energy 4.2 SoC with Audio CODEC

DA14582
Bluetooth Low Energy 4.2 SoC with Audio CODEC
FINAL
• Programming of the Bluetooth device address
• Programming of the trimming value for the external
16 MHz crystal.
This mode of operation applies to the final product and
is performed by the customer. During this phase, cer-
tain fields in the OTP should be programmed
4.5 POWER MODES
There are four different power modes in the DA14582:
• Active mode: System is active and operates at full
speed.
• Sleep mode: No power gating has been pro-
grammed, the ARM CPU is idle, waiting for an inter-
rupt. PD_SYS is on. PD_PER and PED_RAD
depending on the programmed enabled value.
• Extended Sleep mode: All power domains are off
except for the PD_AON, the programmed PD_RRx
and the PD_SR. Since the SysRAM retains its data,
no OTP mirroring is required upon waking up the
system.
• Deep Sleep mode: All power domains are off except
for the PD_AON and the programmed PD_RRx.
This mode dissipates the minimum leakage power.
However, since the SysRAM has not retained its
data, an OTP mirror action is required upon waking
up the system.
4.6 INTERFACES
4.6.1 UARTs
The UART is compliant to the industry-standard 16550
and is used for serial communication with a peripheral,
modem (data carrier equipment, DCE) or data set.
Data is written from a master (CPU) over the APB bus
to the UART and it is converted to serial form and
transmitted to the destination device. Serial data is also
received by the UART and stored for the master (CPU)
to read back.
There is no DMA support on the UART block since its
contains internal FIFOs. Both UARTs support hardware
flow control signals (RTS, CTS, DTR, DSR).
Features
• 16 bytes Transmit and receive FIFOs
• Hardware flow control support (CTS/RTS)
• Shadow registers to reduce software overhead and
also include a software programmable reset
• Transmitter Holding Register Empty (THRE) inter-
rupt mode
• IrDA 1.0 SIR mode supporting low power mode.
• Functionality based on the 16550 industry standard:
• Programmable character properties, such as num-
ber of data bits per character (5-8), optional
• parity bit (with odd or even select) and number of
stop bits (1, 1.5 or 2)
• Line break generation and detection
• Prioritized interrupt identification
• Programmable serial data baud rate as calculated
by the following: baud rate = (serial clock frequency)/
(divisor).
4.6.2 SPI+
This interface supports a subset of the Serial Periph-
eral Interface SPI^TM. The serial interface can transmit
and receive 8, 16 or 32 bits in master/slave mode and
transmit 9 bits in master mode. The SPI + interface has
enhanced functionality with bidirectional 2x16-bit word
FIFOs.
SPI™ is a trademark of Motorola, Inc.
Features
• Slave and Master mode
• 8 bit, 9 bit, 16 bit or 32 bit operation
• Clock speeds up to 16 MHz for the SPI controller.
Programmable output frequencies of SPI source
clock divided by 1, 2, 4, 8
• SPI clock line speed up to 8 MHz
• SPI mode 0, 1, 2, 3 support (clock edge and phase)
• Programmable SPI_DO idle level
• Maskable Interrupt generation
• Bus load reduction by unidirectional writes-only and
reads-only modes.
Built-in RX/TX FIFOs for continuous SPI bursts.
4.6.3 I2C Interface
The I2C interface is a programmable control bus that
provides support for the communications link between
Integrated Circuits in a system. It is a simple two-wire
bus with a software-defined protocol for system control,
which is used in temperature sensors and voltage level
translators to EEPROMs, general-purpose I/O, A/D
and D/A converters.
Features
• Two-wire I2C serial interface consists of a serial data
line (SDA) and a serial clock (SCL)
• Two speeds are supported:
• Standard mode (0 to 100 kbit/s)
• Fast mode (<= 400 kbit/s)
• Clock synchronization
• 32 deep transmit/receive FIFOs
• Master transmit, Master receive operation
• 7 or 10-bit addressing
Datasheet
CFR0011-120-01
Revision 3.0
12 of 172
08-Nov-2016
© 2015 Dialog Semiconductor