DA14581_16 Datasheet, PDF (103/153 Pages) Dialog Semiconductor – Bluetooth Low Energy 4.2 SoC with Optimized Boot Time

DA14581
Bluetooth Low Energy 4.2 SoC with Optimized Boot Time
FINAL
Table 144: I2C_CLR_INTR_REG (0x50001340)
Bit
Mode Symbol
15:1 -
-
0
r
CLR_INTR
Description
Reserved
Read this register to clear the combined interrupt, all individ-
ual interrupts, and the I2C_TX_ABRT_SOURCE register.
This bit does not clear hardware clearable interrupts but soft-
ware clearable interrupts. Refer to Bit 9 of the
I2C_TX_ABRT_SOURCE register for an exception to clear-
ing I2C_TX_ABRT_SOURCE
Reset
0x0
0x0
Table 145: I2C_CLR_RX_UNDER_REG (0x50001344)
Bit
Mode Symbol
15:1 -
-
0
r
CLR_RX_UNDER
Description
Reserved
Read this register to clear the RX_UNDER interrupt (bit 0) of
the
I2C_RAW_INTR_STAT register.
Reset
0x0
0x0
Table 146: I2C_CLR_RX_OVER_REG (0x50001348)
Bit
Mode Symbol
15:1 -
-
0
r
CLR_RX_OVER
Description
Reserved
Read this register to clear the RX_OVER interrupt (bit 1) of
the
I2C_RAW_INTR_STAT register.
Reset
0x0
0x0
Table 147: I2C_CLR_TX_OVER_REG (0x5000134C)
Bit
Mode Symbol
15:1 -
-
0
r
CLR_TX_OVER
Description
Reserved
Read this register to clear the TX_OVER interrupt (bit 3) of
the I2C_RAW_INTR_STAT register.
Reset
0x0
0x0
Table 148: I2C_CLR_RD_REQ_REG (0x50001350)
Bit
Mode Symbol
15:1 -
-
0
r
CLR_RD_REQ
Description
Reserved
Read this register to clear the RD_REQ interrupt (bit 5) of
the I2C_RAW_INTR_STAT register.
Reset
0x0
0x0
Table 149: I2C_CLR_TX_ABRT_REG (0x50001354)
Bit
Mode Symbol
15:1 -
-
0
r
CLR_TX_ABRT
Description
Reserved
Read this register to clear the TX_ABRT interrupt (bit 6) of
the
IC_RAW_INTR_STAT register, and the
I2C_TX_ABRT_SOURCE register. This also releases the TX
FIFO from the flushed/reset state, allowing more writes to
the TX FIFO. Refer to Bit 9 of the I2C_TX_ABRT_SOURCE
register for an exception to clearing
IC_TX_ABRT_SOURCE.
Reset
0x0
0x0
Datasheet
CFR0011-120-01
Revision 3.2
103 of 153
17-Jan-2017
© 2014 Dialog Semiconductor