Q48SC12050 Datasheet, PDF (12/26 Pages) Delta Electronics, Inc. – 600W DC/DC Power Modules

Figure 19: Circuit configuration for trim-up (increase
output voltage)
If the external resistor is connected between the
TRIM and Vo (+) the output voltage set point
increases (Fig.19) The external resistor value
required to obtain a percentage output voltage
change △% is defined as:
Rtrim _ up  ^{5.11Vo (100   )}  ⁵¹¹ 10.2K
1.225

Ex. When Trim-up +10% (12V×1.1=13.2V)
Rtrim _ up  ^{5.1112 (100 10)}  ⁵¹¹ 10.2  489.3K
1.225 10
10
Care should be taken to ensure that the maximum
output power of the module remains at or below the
maximum rated power.
Note3: see the last page.
Power Good, PG
The module provides a Power Good (PG) signal
which is provided by the IC inside module, voltage
level 3.3V, to indicate that the output voltage is within
the normal output voltage range of the power
module. The PG signal will be de-asserted to a low
state if any condition such as overtemperature,
overcurrent or loss of regulation occurs that would
result in the output voltage going below the normal
voltage range value.
The Vout PG function could be changed via PMBUS.
The command related to Vout PG function are
POWER_GOOD_ON and POWER_GOOD_OFF.
.
Parallel and Droop Current Sharing
The modules are capable of operating in parallel, and
realizing current sharing by droop current sharing
method. There is about 500mV output voltage droop
from 0A to full output Load, and there is no current
sharing pin. By connectting the Vin pin and the Vo pin
of the parallel module together, the current sharing
can be realized automatically.
Viinn++
Voo++
Onn/o/ offf f Module I
Vin
Viinn-
Vo-
Load
Viinn++
Vo+
On/off Module II
Viinn-
Vo-
Figure 20: Parallel and droop current sharing configuration for
no redundancy requirement system
If system has no redundancy requirement, the module
can be parallel directly for higher power without adding
external oring-fet; whereas, If the redundancy function is
required, the external oring-fet should be added.
For a normal parallel operation the following precautions
must be observed:
1. The current sharing accuracy equation is:
X% = | Io – ( Itotal / N ) | / Irated, Where,
Io is the output current of per module;
Itotal is the total load current;
N is parallel module numbers;
Irated is the rated full load current of per module.
2. To ensure a better steady current sharing accuracy,
below design guideline should be followed:
a) The inputs of the converters must be connected to the
same voltage source; and the PCB trace resistance
from Input voltage source to Vin+ and Vin- of each
converter should be equalized as much as possible.
b) The PCB trace resistance from each converter’s
output to the load should be equalized as much as
possible.
c) For accurate current sharing accuracy test, the
module should be soldered in order to avoid the
unbalance of the touch resistance between the modules
to the test board.
3. To ensure the parallel module can start up
monotonically without trigging the OCP circuit, below
design guideline should be followed:
a) Before all the parallel module finished start up, the
total load current should be lower than the rated current
of 1 module.
b) The ON/OFF pin of the converters should be
connected together to keep the parallel modules start up
at the same time.
c) The under voltage lockout point will slightly vary from
unit to unit. The dv/dt of the rising edge of the input
source voltage must be greater than 1V/ms to ensure
that the parallel module start up at the same time.
DS_Q48SC12050_03312017
E-mail: [e-mail]
http://www.deltaww.com/dcdc
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