DP80390XP Datasheet, PDF (5/13 Pages) Digital Core Design – Pipelined High Performance 8-bit Microcontroller

BLOCK DIAGRAM
prgramdata(7:0)
prgromdata(7:0)
prgaddr(15:0)
prgdatao(7:0)
prgramwr
xramaddr(23:0)
xdatao(7:0)
xdatai(7:0)
xramdataz
ready
xprgrd
xprgwr
xdatard
xdatawr
Opcode
decoder
Program
memory
interface
External
memory
interface
iprgromsize(2:0)
iprgramsize(2:0)
ramaddr(7:0)
ramdatao(7:0)
ramdatai(7:0)
ramwe
ramoe
sfraddr(6:0)
sfrdatao(7:0)
sfrdatao(7:0)
sfroe
sfrwe
Control
Unit
Internal data
memory
interface
User SFR’s
interface
Floating
Point Unit
t2
t2ex
capture0
capture1
capture2
capture3
rxd1o
rxd1i
txd1
Timer 2
Compare
Capture
UART 1
MDU32
sclhs
scli
sclo
sdai
sdao
clk
reset
rsto
Master/
Slave I2C
Unit
I/O Port
registers
Timers
UART
Interrupt
controller
port0(7:0)
port1(7:0)
port2(7:0)
port3(7:0)
t0
t1
gate0
gate1
rxdi
rxdo
txd
int0
int1
int2
int3
int4
int5
int6
Power
Manage-
ment Unit
stop
pmm
DoCD™
Debug Unit
SXDM
interface
tdi
tck
tms
tdo
rtck
coderun
debugacs
sxdmaddr
sxdmdatao
sxdmdatai
sxdmoe
sxdmwe
Watchdog
Timer
UART 0
SPI Unit
ALU
rxd0o
rxd0i
txd0
so
si
mo
mi
scko
scki
scken
ss
sso(7:0)
soen
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PINS DESCRIPTION
PIN
TYPE
DESCRIPTION
clk
input Global clock
reset
input Global reset
port0i[7:0]
input Port 0 input
port1i[7:0]
input Port 1 input
port2i[7:0]
input Port 2 input
port3i[7:0]
input Port 3 input
iprgramsize[2:0] input Size of on-chip RAM CODE
iprgromsize[2:0] input Size of on-chip ROM CODE
prgramdata[7:0] input Data bus from int. RAM prog. memory
prgromdata[7:0] input Data bus from int. ROM prog. memory
sxdmdatai[7:0]
input Data bus from sync external data
memory (SXDM)
xdatai[7:0]
input Data bus from external memories
ready
input External memory data ready
ramdatai[7:0]
input Data bus from internal data memory
sfrdatai[7:0]
input Data bus from user SFR’s
int0
input External interrupt 0
int1
input External interrupt 1
int2
input External interrupt 2
int3
input External interrupt 3
int4
input External interrupt 4
int5
input External interrupt 5
int6
input External interrupt 6
t0
input Timer 0 input
t1
input Timer 1 input
t2
input Timer 2 input
gate0
input Timer 0 gate input
gate1
input Timer 1 gate input
t2ex
input Timer 2 gate input
capture0
input Timer 2 capture 0 line
capture1
input Timer 2 capture 1 line
capture2
input Timer 2 capture 2 line
capture3
input Timer 2 capture 3 line
rxdi0
input Serial receiver input 0
rxdi1
input Serial receiver input 1
scli
input Master/Slave I2C clock line input
sdai
input Master/Slave I2C data input
ss
input SPI slave select
si
input SPI slave input
mi
input SPI master input
scki
input SPI clock input
tdi
input DoCD™ TAP data input
tck
input DoCD™ TAP clock input
tms
input DoCD™ TAP mode select input
rsto
output Reset output
port0o[7:0]
output Port 0 output
port1o[7:0]
output Port 1 output
port2o[7:0]
output Port 2 output
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