DFPAU Datasheet, PDF (4/5 Pages) Digital Core Design – Floating Point Arithmetic Coprocessor

IMPROVEMENTS
DFPAU floating point instructions perform-
ance has been compared to standard C li-
brary functions delivered with every commer-
cial C compiler. Each program was executed
in the same system environments. Number of
clock periods were measured between input
data loading into work registers and output
result storing after operation. The results are
placed in table below. Improvement has been
computed as number of:
(CPU clk) divided by (CPU+DFPAU clk), re-
quired to execute the same operation.
More details are available in core docu-
mentation.
The following table gives a survey about
the DP8051+DFPAU performance compared
to std 8051 microcontroller.
Device
Improvement
80C51
1.0
DP8051
7.3
DP8051+DFPAU
91.0
General performance improvements
150
The table below shows performance im-
provements of the NIOS-II processor with
DFPAU, compared to the same system with-
out the DFPAU coprocessor.
Device
Improvement
NIOS-II/s
1.0
NIOS-II+DFPAU (arithmetic)
7.5
NIOS-II+DFPAU (trigonometric)
5.9
NIOS-II+DFPAU (overall)
6.8
General performance improvements
12
8
7,5
6,8
5,9
4
1
0
32-bit NIOS-II/s
NIOS-II+DFPAU (arithmetic)
NIOS-II+DFPAU (trigonometric)
NIOS-II+DFPAU (overall)
100
50
0
80C51
91
1
7,3
DP8051
DP8051+DFPAU
IEEE-754 FP Instruction
Improvement
Addition
6.4
Subtraction
6.5
Multiplication
5.1
Division
6.5
Square Root
12.9
Sine
5.2
Cosine
5.4
Tangent
5.8
Arcs Tangent
7.2
Average speed improvement:
6.8
Improvements of particular operations
IEEE-754 FP Instruction
Improvement
Addition
73
Subtraction
60
Multiplication
65
Division
182
Square Root
392
Sine
10
Cosine
10
Tangent
12
Arcs Tangent
17
Average speed improvement:
91
Improvements of particular operations
More details are available in core docu-
mentation.
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