DFPAU Datasheet, PDF (3/5 Pages) Digital Core Design – Floating Point Arithmetic Coprocessor

SYMBOL
datai(31:0)¹
addr(4:2)²
we
datao(31:0)¹
irq
cs
rst
clk
PINS DESCRIPTION
PIN
clk
rst
cs
datai[31:0]¹
addr[4:2]²
we
datao[31:0]¹
int
TYPE
DESCRIPTION
Input Global system clock
Input Global system reset
Input Chip select for read/write
Input Data bus input
Input Register address to read/write
Input Data write enable
Output Data bus output
Output Interrupt request indicator
1 – data bus can be configured as 8-, 16- or 32- bit
depends on processor’s bus size
2 – address bus is aligned to work with 8- (3:0), 16-
(3:1) or 32- (4:2) bit processors
BLOCK DIAGRAM
Mantissa – performs operations on mantissa
part of number. The addition, subtraction,
multiplication, division, square root, compari-
son and conversion operations are executed
in this module. It contains mantissas and
work registers.
Exponent – performs operations on expo-
nent part of number. The addition, subtrac-
tion, shifting, comparison and conversion
operations are executed in this module. It
contains exponents and work registers.
Align – performs the numbers analyze
against IEEE-754 standard compliance. In-
formation about the data classes are passed
as result to appropriate internal module.
Shifter – performs mantissa shifting during
normalization, denormalization operations.
Information about shifted-out bits are stored
for rounding process.
Control Unit – manages execution of all
instructions and internal operation required to
execute particular function.
datai(31:0)¹
datao(31:0)¹
irq
addr(4:2)²
we
cs
Interface
Mantissa
Align
Exponent
Shifter
clk
Control
rst
Unit
Interface – makes interface between exter-
nal device and DFPAU internal 32-bit mod-
ules. It contains data, control and status reg-
isters. It can be configured to work with 8-,
16- and 32-bit processors.
PERFORMANCE
The following table gives a survey about
the Core area and performance in the AL-
TERA® devices after Place & Route (all key
features have been included):
Device
Speed
grade
Logic Cells
F_max
APEX20KE
-1
2640
48 MHz
APEX20KC
-7
2640
57 MHz
APEX-II
-7
2640
70 MHz
CYCLONE
-6
2410
91 MHz
CYCLONE-II
-6
2280
96 MHz
STRATIX
-5
2210
115 MHz
STRATIX-II
-3
1680
169 MHz
Core performance in ALTERA® devices
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