DFPSQRT Datasheet, PDF (1/3 Pages) Digital Core Design – Floating Point Pipelined Square Root Unit

DFPSQRT
Floating Point Pipelined Square Root Unit
ver 2.90
OVERVIEW
The DFPSQRT uses the pipelined mathe-
matics algorithm to compute square root
function. The input number format is accord-
ing to IEEE-754 standard. DFPSQRT sup-
ports single precision real numbers. SQRT
operation can be pipelined up to 9 levels.
Input data are fed every clock cycle. The first
result appears after 9 clock periods latency
and next results are available each clock
cycle. Precision and accuracy are parameter-
ized.
APPLICATION
● Math coprocessors
● DSP algorithms
● Embedded arithmetic coprocessor
● Data processing & control
KEY FEATURES
● Full IEEE-754 compliance
● Single precision real format support
● Simple interface
● No programming required
● 9 levels pipelining
● 24-bit accuracy, 6 fractional decimal digits
● Results available at every clock
● Fully configurable
All trademarks mentioned in this document
are trademarks of their respective owners.
♦ Fully synthesizable, static synchronous
design with no internal tri-states
DELIVERABLES
♦ Source code:
◊ VHDL Source Code or/and
◊ VERILOG Source Code or/and
◊ Encrypted, or plain text EDIF netlist
♦ VHDL & VERILOG test bench environ-
ment
◊ Active-HDL automatic simulation mac-
ros
◊ ModelSim automatic simulation macros
◊ NCSim automatic simulation macros
◊ Tests with reference responses
♦ Technical documentation
◊ Installation notes
◊ HDL core specification
◊ Datasheet
♦ Synthesis scripts
♦ Example application
♦ Technical support
◊ IP Core implementation support
◊ 3 months maintenance
● Delivery the IP Core updates, minor
and major versions changes
● Delivery the documentation updates
● Phone & email support
LICENSING
Comprehensible and clearly defined licensing
methods without royalty fees make using of
IP Core easy and simply.
Single Design license allows using IP Core in
single FPGA bitstream and ASIC implemen-
http://www.DigitalCoreDesign.com
http://www.dcd.pl
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