DFPDIV Datasheet, PDF (1/3 Pages) Digital Core Design – Floating Point Pipelined Divider Unit

DFPDIV
Floating Point Pipelined Divider Unit
ver 2.15
OVERVIEW
The DFPDIV uses the pipelined mathemat-
ics algorithm to divide two arguments. The
input numbers format is according to IEEE-
754 standard. DFPDIV supports single preci-
sion real number. Divide operation was pipe-
lined up to 15 levels. Input data are fed every
clock cycle. The first result appears after 15
clock periods latency and next results are
available each clock cycle. Full IEEE-754
precision and accuracy are included.
APPLICATION
● Math coprocessors
● DSP algorithms
● Embedded arithmetic coprocessor
● Data processing & control
KEY FEATURES
● Full IEEE-754 compliance
● Single precision real format support
● Simple interface
● No programming required
● 15 levels pipeline
● Full accuracy and precision
● Results available at every clock
● Overflow, underflow and invalid operation
flags
● Fully configurable
● Fully synthesizable, static synchronous
design with no internal tri-states
DELIVERABLES
♦ Source code:
◊ VHDL Source Code or/and
◊ VERILOG Source Code or/and
◊ Encrypted, or plain text EDIF netlist
♦ VHDL & VERILOG test bench environ-
ment
◊ Active-HDL automatic simulation mac-
ros
◊ NCSim automatic simulation macros
◊ ModelSim automatic simulation macros
◊ Tests with reference responses
♦ Technical documentation
◊ Installation notes
◊ HDL core specification
◊ Datasheet
♦ Synthesis scripts
♦ Example application
♦ Technical support
◊ IP Core implementation support
◊ 3 months maintenance
● Delivery the IP Core updates, minor
and major versions changes
● Delivery the documentation updates
● Phone & email support
LICENSING
Comprehensible and clearly defined licensing
methods without royalty fees make using of
IP Core easy and simply.
Single Design license allows using IP Core in
single FPGA bitstream and ASIC implemen-
All trademarks mentioned in this document
are trademarks of their respective owners.
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