DM9302 Datasheet, PDF (19/64 Pages) Davicom Semiconductor, Inc. – 10/100Mbps Ethernet Fiber/Twisted Pair Media Converter with Local bus

DM9302
10/100Mbps Ethernet Fiber/Twisted Pair Media Converter with Local bus
3
EPOS PH0,RW EEPROM or PHY Operation Select
When reset, select EEPROM; when set, select PHY
2
ERPRR PH0,RW EEPROM Read or PHY Register Read Command. Driver needs to clear it up after
the operation completes.
1
ERPRW PH0,RW EEPROM Write or PHY Register Write Command. Driver needs to clear it up after
the operation completes.
0
ERRE
PH0,RO EEPROM Access Status or PHY Access Status
When set, it indicates that the EEPROM or PHY access is in progress
6.9 EEPROM & PHY Address Register (0CH)
Bit
Name
Default
Description
7:6 PHY_ADR PH01,RW PHY Address bit 1 and 0; the PHY address bit [4:2] is force to 0.
5:0
EROA PH0,RW EEPROM Word Address or PHY Register Address
6.10 EEPROM & PHY Data Registers (0DH~0EH)
Bit
Name
Default
Description
7:0
EPDRL PH0,RW EEPROM or PHY Low Byte Data (0DH)
This data is made to write/read low byte of word address defined in Reg. 0CH to
EEPROM or PHY
7:0
EPDRH PH0,RW EEPROM or PHY High Byte Data (0EH)
This data is made to write/read high byte of word address defined in Reg. 0CH to
EEPROM or PHY
6.11 Link Change Control Register (0FH)
Bit
Name
Type
Description
7:6 RESERVED 0,RO Reserved
5
LINKEN
PE0,RW Link Change Event Enable
When both set of this bit and bit 6 of NCR, it enables link change status Event
4:3 RESERVED 0,RO Reserved
2
LINKST
PH0,RO Link Change Event Status
When set, it indicates that Link Status Change Event (link of port 0 or 1) occurred
This bit can be cleared by write 1 to bit 5 of NSR or write 0 to bit 6 of NCR.
1:0 RESERVED 0,RO Reserved
6.12 Processor Port Physical Address Registers (10H~15H)
Bit
Name
Default
7:0
PAB5
E,RW Physical Address Byte 5 (15H)
7:0
PAB4
E,RW Physical Address Byte 4 (14H)
7:0
PAB3
E,RW Physical Address Byte 3 (13H)
7:0
PAB2
E,RW Physical Address Byte 2 (12H)
7:0
PAB1
E,RW Physical Address Byte 1 (11H)
7:0
PAB0
E,RW Physical Address Byte 0 (10H)
Description
6.13 Processor Port Multicast Address Registers (16H~1DH)
Bit
Name
Default
7:0
MAB7
X,RW Multicast Address Byte 7 (1DH)
7:0
MAB6
X,RW Multicast Address Byte 6 (1CH)
7:0
MAB5
X,RW Multicast Address Byte 5 (1BH)
Description
Preliminary datasheet
19
DM9302-15-DS-P01
July 30, 2009