DM9010BI Datasheet, PDF(14/60 Page) Davicom Semiconductor, Inc. – Industrial-temperature 10/100 Mbps Single Chip Ethernet Controller With General Processor Interface

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DM9010BI Datasheet, PDF (14/60 Pages) Davicom Semiconductor, Inc. – Industrial-temperature 10/100 Mbps Single Chip Ethernet Controller With General Processor Interface

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DM9010BI

Industrial-temperature Single Chip Ethernet Controller with General Processor Interface

6. VENDOR CONTROL AND STATUS REGISTER SET

The DM9010BI implements several control and status

registers, which can be accessed by the host. These CSRs

are byte aligned. All CSRs are set to their default values by

hardware or software reset unless they are specified

Description

NCR

NSR

TCR

TSR I

TSR II

RCR

RSR

ROCR

BPTR

FCTR

FCR

EPCR

EPAR

EPDRL

EPDRH

WCR

PAR

Network Control Register

Network Status Register

TX Control Register

TX Status Register I

TX Status Register II

RX Control Register

RX Status Register

Receive Overflow Counter Register

Back Pressure Threshold Register

Flow Control Threshold Register

RX Flow Control Register

EEPROM & PHY Control Register

EEPROM & PHY Address Register

EEPROM & PHY Low Byte Data Register

EEPROM & PHY High Byte Data Register

Wake Up Control Register

Physical Address Register

MAR

GPCR

GPR

TRPAL

TRPAH

RWPAL

RWPAH

VID

PID

CHIPR

TCR2

OCR

SMCR

ETXCSR

TCSCR

RCSCSR

EPADR

GPCR2

GPR2

GPCR3

GPR3

Multicast Address Register

General Purpose Control Register

General Purpose Register

TX SRAM Read Pointer Address Low Byte

TX SRAM Read Pointer Address High Byte

RX SRAM Write Pointer Address Low Byte

RX SRAM Write Pointer Address High Byte

Vendor ID

Product ID

CHIP Revision

TX Control Register 2

Operation Control Register

Special Mode Control Register

Early Transmit Control/Status Register

Transmit Check Sum Control Register

Receive Check Sum Control Status Register

External PHY address

General Purpose Control Register 2

General Purpose Register 2

General Purpose Control Register 3

General Purpose Register 3

Offset

00H

01H

02H

03H

04H

05H

06H

07H

08H

09H

0AH

0BH

0CH

0DH

0EH

0FH

10H-15H

16H-1DH

1EH

1FH

22H

23H

24H

25H

28H-29H

2AH-2BH

2CH

2DH

2EH

2FH

30H

31H

32H

33H

34H

35H

36H

37H

Default value

after reset

00H

37H

38H

00H

40H

XXH

00H

Determined by

EEPROM

XXH

01H

XXH

00H

0CH

0A46H

9000H

12H

00H

01H

00H

Preliminary

Version: DM9010BI--DS-P01

January 12, 2010

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