DM9010BI Datasheet, PDF (12/60 Pages) Davicom Semiconductor, Inc. – Industrial-temperature 10/100 Mbps Single Chip Ethernet Controller With General Processor Interface

5.6 10/100 PHY/Fiber
24
SD
25
26
27,28
29
30
31
32
33
34
35
BGGND
BGRES
RXVDD18
RXI+
RXI-
RXGND
TXGND
TXO+
TXO-
TXVDD18
DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
I Fiber-optic Signal Detect
PECL signal, which indicates whether or not the fiber-optic receive pair is
receiving valid levels
P Band gap Ground, need to connect to AGND.
I/O Band gap Pin
P Internal regulator 1.8V output for TP RX
I/O TP RX Input
I/O TP RX Input
P RX Ground
P TX Ground
I/O TP TX Output
I/O TP TX Output
P Internal regulator 1.8V output for TP TX
5.7 Miscellaneous
16,17,18, TEST1~TEST4
19
I Operation Mode
Test 1, 2, 3, 4 = (1, 1, 0, 0) in normal application
48
TEST5
68,69,70,
71,
74,75,77
GP0~6
78
LINK_O
79
WAKE
80
PW_RST#
36
NC
I,PD Internal system clock source
0: use internal 50MHz clock *(Suggestion)
1: use CLK20MO pin
I/O,PD General I/O Ports
Registers GPCR and GPR can program these pins
The GPIO0 is an output mode, and output data high at default is to power
down internal PHY and other external MII device
GP1~3 defaults are input ports, GP 0, 4~6 force to output ports.
O,PD Cable Link Status Output. Active High
This pin is also used as a strap pin to define whether the MII interface is a
reversed MII interface (pulled high) or a normal MII interface (not pulled
high). This pin has a pulled down resistor about 60k ohm internally.
O,PD Issue a wake up signal when wake up event happens
This pin has a pulled down resistor about 60k ohm internally.
I Power on Reset
Active low signal to initiate the DM9010BI
The DM9010BI is ready after 5us when this pin deasserted
NC NC
Preliminary
12
Version: DM9010BI--DS-P01
January 12, 2010