3D7701 Datasheet, PDF (3/4 Pages) Data Delay Devices, Inc. – MONOLITHIC GATED DELAY LINE OSCILLATOR

3D7701
APPLICATION NOTES (CONT’D)
POWER SUPPLY AND
TEMPERATURE CONSIDERATIONS
The delay of CMOS integrated circuits is strongly
dependent on power supply and temperature.
The monolithic 3D7701 oscillator utilizes novel
and innovative compensation circuitry to
minimize the frequency variations induced by
fluctuations in power supply and/or temperature.
The thermal coefficient is reduced to 250 PPM/C,
which is equivalent to a variation, over the -40C
to 85C operating range, of ±1.5% from the room-
temperature frequency setting. The power supply
coefficient is reduced, over the 4.75V to 5.25V
operating range, to ±0.5% of the frequency
setting at the nominal 5.0VDC power supply.
These specifications hold for the lower
frequencies only. For higher dash numbers, the
variations will be slightly greater, as noted in
Table 1. It is essential that the power supply
pin be adequately bypassed and filtered. In
addition, the power bus should be of as low
an impedance construction as possible.
Power planes are preferred.
DEVICE SPECIFICATIONS
TABLE 2: ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL MIN
MAX UNITS NOTES
DC Supply Voltage
V_DD
-0.3
7.0
V
Input Pin Voltage
V_IN
-0.3
V_DD+0.3
V
Input Pin Current
I_IN
-1.0
1.0
mA
25C
Storage Temperature
T_STRG
-55
150
C
Lead Temperature
T_LEAD
300
C
10 sec
TABLE 3: DC ELECTRICAL CHARACTERISTICS
(-40C to 85C, 4.75V to 5.25V)
PARAMETER
SYMBOL MIN
Static Supply Current*
I_DD
High Level Input Voltage
V_IH
2.0
Low Level Input Voltage
V_IL
High Level Input Current
I_IH
Low Level Input Current
I_IL
High Level Output
I_OH
Current
Low Level Output Current
I_OL
4.0
Output Rise & Fall Time
T_R & T_F
TYP
3.5
-35.0
15.0
2.0
MAX
5.5
0.8
1.0
1.0
-4.0
2.5
UNITS
mA
V
V
µA
µA
mA
mA
ns
NOTES
V_IH = V_DD
V_IL = 0V
V_DD = 4.75V
V_OH = 2.4V
V_DD = 4.75V
V_OL = 0.4V
C_LD = 5 pf
*I_DD(Dynamic) = 2 * C_LD * V_DD * F
where: C_LD = Average capacitance load/output (pf)
F = Device frequency (GHz)
Input Capacitance = 10 pf typical
Output Load Capacitance (C_LD) = 25 pf max
Doc #06023
DATA DELAY DEVICES, INC.
3
12/5/2006
3 Mt. Prospect Ave. Clifton, NJ 07013