3D3444 Datasheet, PDF (3/6 Pages) Data Delay Devices, Inc. – MONOLITHIC QUAD 4-BIT PROGRAMMABLE DELAY LINE (SERIES 3D3444)

3D3444
PROGRAMMED DELAY (ADDRESS)
UPDATE
A delay line is a memory device. It stores
information present at the input for a time equal
to the delay setting before presenting it at the
output with minimal distortion. Each 4-bit delay
line in the 3D3444 can be represented by 15
serially connected delay elements (individually
addressed by the programming data), each
capable of storing data for a time equal to the
device increment (step time). The delay line
memory property, in conjunction with the
operational requirement of “instantaneously”
connecting the delay element addressed by the
programming data to the output, may inject
spurious information onto the output data stream.
In order to ensure that spurious outputs do not
occur, it is essential that the input signal be idle
(held high or low) for a short duration prior to
updating the programmed delay. This duration is
given by the maximum programmable delay.
Satisfying this requirement allows the delay line
to “clear” itself of spurious edges. When the new
address is loaded, the input signal can begin to
switch (and the new delay will be valid) after a
time given by t_PDV or t_EDV (see section below).
LATCH
(AL)
t_CW t_CW
CLOCK
(SC)
SERIAL
INPUT
(SI)
t_DSC
NEW
BIT 1
SERIAL
OUTPUT
(SO)
OLD
BIT 1
t_DHC
NEW
BIT 2
t_PCQ
OLD
BIT 2
DELAY
TIMES
PREVIOUS VALUES
POWER SUPPLY AND
TEMPERATURE CONSIDERATIONS
The delay of CMOS integrated circuits is strongly
dependent on power supply and temperature.
The monolithic 3D3444 programmable delay line
utilizes novel and innovative compensation
circuitry to minimize the delay variations induced
by fluctuations in power supply and/or
temperature.
The thermal coefficient is reduced to 400
PPM/C, which is equivalent to a variation, over
the 0C-70 C operating range, of ±2% from the
room-temperature delay settings. The power
supply coefficient is reduced, over the 3.0V-
3.6V operating range, to ±1.5% of the delay
settings at the nominal 3.3VDC power supply
and/or ±2ns, whichever is greater.
It is essential that the power supply pin be
adequately bypassed and filtered. In addition,
the power bus should be of as low an
impedance construction as possible. Power
planes are preferred.
t_LW
t_CSL
NEW
BIT 20
OLD
BIT 20
t_LDX
NEW
BIT 1
t_LDV
NEW
VALUES
Figure 2: Serial interface timing diagram
FROM
WRITING
DEVICE
3D3444
SI
SO
SC AL
3D3444
SI
SO
SC AL
3D3444
SI
SO
SC AL
TO
NEXT
DEVICE
Figure 3: Cascading Multiple Devices
Doc #00119
DATA DELAY DEVICES, INC.
3
8/2/02
3 Mt. Prospect Ave. Clifton, NJ 07013