3D3444 Datasheet, PDF (2/6 Pages) Data Delay Devices, Inc. – MONOLITHIC QUAD 4-BIT PROGRAMMABLE DELAY LINE (SERIES 3D3444)

3D3444
APPLICATION NOTES
THEORY OF OPERATION
The quad 4-bit programmable 3D3444 delay line
architecture is comprised of a number of delay
cells connected in series with their respective
outputs multiplexed onto the Delay Out pin (O1-
O4) by the user-selected programming data.
Each delay cell produces at its output a replica of
the signal present at its input, shifted in time.
Each of the four lines can be controlled
independently, via the serial interface.
PROGRAMMED DELAY (ADDRESS)
INTERFACE
Figure 1 illustrates the main functional blocks of
the 3D3444 device. Since the device is a CMOS
design, all unused input pins must be returned to
well defined logic levels (VDD or GND). The
delays are adjusted by first shifting a 20-bit
programming word into the device via the SC and
SI pins, then strobing the AL signal to latch the
values. The bit sequence is shown in Table 2,
and the associated timing diagram is shown in
Figure 2. Each line has associated with it an
enable bit. Setting this bit low will force the
corresponding delay line output to a high
impedance state, while setting it high returns the
line to its normal operation. The device contains
an SO output, which can be used to cascade
multiple devices, as shown in Figure 3.
TABLE 2: BIT SEQUENCE
Bit Delay Function
Line
14
Output Enable
23
Output Enable
32
Output Enable
41
Output Enable
51
Address Bit 3
6
Address Bit 2
7
Address Bit 1
8
Address Bit 0
92
Address Bit 3
10
Address Bit 2
11
Address Bit 1
12
Address Bit 0
13 3
Address Bit 3
14
Address Bit 2
15
Address Bit 1
16
Address Bit 0
17 4
Address Bit 3
18
Address Bit 2
19
Address Bit 1
20
Address Bit 0
I4
DELAY
LINE
I3
DELAY
LINE
I2
DELAY
LINE
I1
DELAY
LINE
ADDR4
ADDR3
ADDR2
ADDR1 ENABLES
AL
20-BIT LATCH
SI
SC
20-BIT SHIFT REGISTER
Figure 1: Functional block diagram
Doc #00119
DATA DELAY DEVICES, INC.
8/2/02
Tel: [phone] Fax: [phone] http://www.datadelay.com
O4
O3
O2
O1
SO
2