3D3323 Datasheet, PDF (3/4 Pages) Data Delay Devices, Inc. – MONOLITHIC TRIPLE FIXED DELAY LINE

3D3323
APPLICATION NOTES (CONT’D)
custom reference designator identifying the
intended frequency and duty cycle of operation.
The programmed delay accuracy of the device is
guaranteed, therefore, only for the user specified
input characteristics. Small input pulse width
variation about the selected pulse width will only
marginally impact the programmed delay
accuracy, if at all. Nevertheless, it is strongly
recommended that the engineering staff at
DATA DELAY DEVICES be consulted.
POWER SUPPLY AND
TEMPERATURE CONSIDERATIONS
The delay of CMOS integrated circuits is strongly
dependent on power supply and temperature.
The monolithic 3D3323 programmable delay line
utilizes novel and innovative compensation
circuitry to minimize the delay variations induced
by fluctuations in power supply and/or
temperature.
The thermal coefficient is reduced to 300
PPM/C, which is equivalent to a variation , over
the -40C to 85C operating range, of ±3% from
the room-temperature delay settings and/or
1.0ns, whichever is greater. The power supply
coefficient is reduced, over the 3.0V to 3.6V
operating range, to ±1% of the delay settings at
the nominal 3.3VDC power supply and/or 2.0ns,
whichever is greater. It is essential that the
power supply pin be adequately bypassed
and filtered. In addition, the power bus
should be of as low an impedance
construction as possible. Power planes are
preferred.
DEVICE SPECIFICATIONS
TABLE 2: ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL MIN
MAX UNITS NOTES
DC Supply Voltage
Input Pin Voltage
Input Pin Current
Storage Temperature
Lead Temperature
V_DD
V_IN
I_IN
T_STRG
T_LEAD
-0.3
7.0
V
-0.3
V_DD+0.3
V
-1.0
1.0
mA
25C
-55
150
C
300
C
10 sec
TABLE 3: DC ELECTRICAL CHARACTERISTICS
(-40C to 85C, 3.0V to 3.6V)
PARAMETER
SYMBOL MIN
Static Supply Current*
I_DD
High Level Input Voltage
V_IH
2.0
Low Level Input Voltage
V_IL
High Level Input Current
I_IH
-1
Low Level Input Current
I_IL
-1
High Level Output Current
I_OH
Low Level Output Current
I_OL
4.0
Output Rise & Fall Time
T_R & T_F
MAX
5
0.8
1
1
-4.0
2
UNITS
mA
V
V
µA
µA
mA
mA
ns
NOTES
V_IH = V_DD
V_IL = 0V
V_DD = 4.75V
V_OH = 2.4V
V_DD = 4.75V
V_OL = 0.4V
C_LD = 5 pf
*I_DD(Dynamic) = 3 * C_LD * V_DD * F
where: C_LD = Average capacitance load/line (pf)
F = Input frequency (GHz)
Input Capacitance = 10 pf typical
Output Load Capacitance (C_LD) = 25 pf max
Doc #06017
DATA DELAY DEVICES, INC.
3
5/10/2006
3 Mt. Prospect Ave. Clifton, NJ 07013