PDU1064H Datasheet, PDF (2/5 Pages) Data Delay Devices, Inc. – 6-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE (SERIES PDU1064H)

PDU1064H
APPLICATION NOTES
ADDRESS UPDATE
The PDU1064H is a memory device. As such,
special precautions must be taken when
changing the delay address in order to prevent
spurious output signals. The timing restrictions
are shown in Figure 1.
After the last signal edge to be delayed has
appeared on the OUT pin, a minimum time,
T_OAX, is required before the address lines can
change. This time is given by the following
relation:
T_OAX = max { (A_i - A _i-1) * T_INC , 0 }
where A _i-1 and A_i are the old and new address
codes, respectively. Violation of this constraint
may, depending on the history of the input signal,
cause spurious signals to appear on the OUT
pin. The possibility of spurious signals persists
until the required T_OAX has elapsed.
A similar situation occurs when using the ENB
signal to disable the output while IN is active. In
this case, the unit must be held in the disabled
state until the device is able to “clear” itself. This
is achieved by holding the ENB signal high and
the IN signal low for a time given by:
T_DISH = A_i * T_INC
Violation of this constraint may, depending on
the history of the input signal, cause spurious
signals to appear on the OUT pin. The
possibility of spurious signals persists until the
required T_DISH has elapsed.
INPUT RESTRICTIONS
There are three types of restrictions on input
pulse width and period listed in the AC
Characteristics table. The recommended
conditions are those for which the delay
tolerance specifications and monotonicity are
guaranteed. The suggested conditions are
those for which signals will propagate through the
unit without significant distortion. The absolute
conditions are those for which the unit will
produce some type of output for a given input.
When operating the unit between the
recommended and absolute conditions, the
delays may deviate from their values at low
frequency. However, these deviations will
remain constant from pulse to pulse if the input
pulse width and period remain fixed. In other
words, the delay of the unit exhibits frequency
and pulse width dependence when operated
beyond the recommended conditions. Please
consult the technical staff at Data Delay Devices
if your application has specific high-frequency
requirements.
Please note that the increment tolerances listed
represent a design goal. Although most delay
increments will fall within tolerance, they are not
guaranteed throughout the address range of the
unit. Monotonicity is, however, guaranteed over
all addresses.
A5-A0
ENB
IN
OUT
T_AENS
A _i-1
A_i
T_OAX
T_AIS
T_ENIS
PW_IN
T_DISH
TD_A
PW_OUT
T_DISO
Figure 1: Timing Diagram
Doc #97046
DATA DELAY DEVICES, INC.
2
12/17/97
Tel: [phone] Fax: [phone] http://www.datadelay.com