3D7438 Datasheet, PDF (2/6 Pages) Data Delay Devices, Inc. – MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE (SERIES 3D7438)

3D7438
APPLICATION NOTES
GENERAL INFORMATION
The 8-bit programmable 3D7438 delay line
architecture is comprised of a sequence of five
identical delay cells connected in series, all of
which are controlled by a common current. This
current, in turn, is controlled by the user-selected
programming data (the address). The delay cells
produce at their output a replica of the signal
present at the input, shifted in time. The change
in delay from one address setting to the next is
called the increment, or LSB. It is nominally equal
to the device dash number. The minimum delay,
achieved by setting the address to zero, is called
the inherent delay.
where T_inh is the nominal inherent delay. The
absolute error is limited to 1.5 LSB or 1.0 ns,
whichever is greater, at every address.
The inherent delay error is the deviation of the
inherent delay from its nominal value. For all
dash numbers, it is limited to 0.5 ns.
DELAY STABILITY
The delay of CMOS integrated circuits is strongly
dependent on power supply and temperature.
The 3D7438 utilizes novel compensation circuitry
to minimize the delay variations induced by
fluctuations in power supply and/or temperature.
For best performance, it is essential that the
power supply pin be adequately bypassed and
filtered. In addition, the power bus should be of
as low an impedance construction as possible.
Power planes are preferred. Also, signal traces
should be kept as short as possible.
DELAY ACCURACY
There are a number of ways of characterizing the
delay accuracy of a programmable line. The first
is the differential nonlinearity (DNL), also referred
to as the increment error. It is defined as the
deviation of the increment at a given address
from its nominal value. For all dash numbers, the
DNL is within 0.5 LSB at every address (see
Table 1: Delay Step).
The integrated nonlinearity (INL) is determined
by first constructing the least-squares best fit
straight line through the delay-versus-address
data. The INL is then the deviation of a given
delay from this line. For all dash numbers, the
INL is within 1.0 LSB at every address.
The relative error is defined as follows:
e_rel = (T_i – T₀) – i * T_inc
where i is the address, T_i is the measured delay
at the i’th address, T₀ is the measured inherent
delay, and T_inc is the nominal increment. It is very
similar to the INL, but simpler to calculate. For all
dash numbers, the relative error is less than 1.0
LSB at every address (see Table 1: Delay
Range).
The absolute error is defined as follows:
e_abs = T_i – (T_inh + i * T_inc)
The 3D7438 is designed to be most stable at the
maximum address setting (255). At this operating
condition, the thermal coefficient of the absolute
delay is limited to 250 PPM/C, which is
equivalent to a variation, over the -40C to 85C
operating range, of 1.5% from the room-
temperature delay. At smaller address settings
the thermal coefficient will be somewhat larger.
At the maximum address, the power supply
sensitivity of the absolute delay is 0.5% over the
4.75V to 5.25V operating range, with respect to
the delay at the nominal 5.0V power supply. At
smaller address settings the sensitivity will be
somewhat larger.
INPUT SIGNAL CHARACTERISTICS
The maximum input frequency and minimum
input pulse width are both limited by the device.
Exceeding either limit will cause the signal to be
blocked by the line. Furthermore, for a given
device, these limitations vary with the user-
specified address. The relationships are:
F_Max = 1250 / (i * T_inc)
PW_Min = 0.4 * (i * T_inc),
where F_Max is in MHz, and PW_Min & T_inc are in ns.
These relationships break down for small delays:
F_Max can never be greater than 150 MHz, and
PW_Min can never be smaller than 3.3 ns.
PROGRAMMING INTERFACE
Figure 1 illustrates the main functional blocks of
the 3D7438 delay program interface. Since the
3D7438 is a CMOS design, all unused input pins
must be returned to well defined logic levels,
VDD or Ground.
Doc #10004
DATA DELAY DEVICES, INC.
2
7/8/2010
Tel: [phone] Fax: [phone] http://www.datadelay.com