DS3101 Datasheet, PDF (89/149 Pages) Dallas Semiconductor – Stratum 3/3E Timing Card IC

DS3101 Stratum 3/3E Timing Card IC
Register Name:
Register Description:
Register Address:
DLIMIT1
DPLL Frequency Limit Register 1
41h
Name
Default
Bit 7
0
Bit 6
1
Bit 5
1
Bit 4
Bit 3
HARDLIM[7:0]
1
0
Bit 2
1
Bit 1
1
Bit 0
0
The DLIMIT1 and DLIMIT2 registers must be read consecutively and written consecutively. See Section 8.3.
Bits 7 to 0: DPLL Hard Frequency Limit (HARDLIM[7:0]). The full 10-bit HARDLIM[9:0] field spans this register
and DLIMIT2. HARDLIM is an unsigned integer that specifies the hard frequency limit or pull-in/hold-in range of the
T0 DPLL. When frequency limit detection is enabled by setting FLLOL = 1 in the DLIMIT3 register, if the DPLL
frequency exceeds the hard limit then the DPLL declares loss-of-lock. The hard frequency limit in ppm is
±HARDLIM[9:0] x 0.078. The default value is normally ±9.2ppm. If external reference switching mode is enabled
during reset (see Section 7.6.5), the default value is configured to ±79.794ppm (3FFh). See Section 7.7.6.
Register Name:
Register Description:
Register Address:
DLIMIT2
DPLL Frequency Limit Register 2
42h
Name
Default
Bit 7
—
0
Bit 6
—
0
Bit 5
—
0
Bit 4
—
0
Bit 3
—
0
Bit 2
—
0
Bit 1
Bit 0
HARDLIM[9:8]
0
0
Bits 1 to 0: DPLL Hard Frequency Limit (HARDLIM[9:8]). See the DLIMIT1 register description.
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