DS3142 Datasheet, PDF (81/88 Pages) Dallas Semiconductor – Single/Dual/Triple/Quad DS3/E3 Framers

DS3141/DS3142/DS3143/DS3144 Single/Dual/Triple/Quad DS3/E3 Framers
11.3 JTAG Interface Timing
Table 11-D. JTAG Interface Timing
(V_DD = 3.3V ±5%, T_A = -40°C to +85°C.) (Figure 11-6)
PARAMETER
SYMBOL
JTCLK Clock Period
t1
JTCLK Clock High/Low Time
t2/t3
JTCLK to JTDI, JTMS Setup Time
t4
JTCLK to JTDI, JTMS Hold Time
t5
JTCLK to JTDO Delay
t6
JTCLK to JTDO High-Z Delay
t7
JTRST Width Low Time
t8
Note 12: Clock can be stopped high or low.
CONDITIONS
(Note 12)
MIN TYP MAX UNITS
1000
ns
50 500
ns
50
ns
50
ns
2
50
ns
2
50
ns
100
ns
Figure 11-6. JTAG Interface Timing Diagram
t1
t2
t3
JTCLK
JTDI, JTMS
JTD0
t6
t7
t4
t5
t8
JTRST
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