DS3142 Datasheet, PDF (76/88 Pages) Dallas Semiconductor – Single/Dual/Triple/Quad DS3/E3 Framers

DS3141/DS3142/DS3143/DS3144 Single/Dual/Triple/Quad DS3/E3 Framers
11.2 Microprocessor Interface Timing
Table 11-C. Microprocessor Interface Timing
(V_DD = 3.3V ±5%, T_A = -40°C to +85°C.) (Figure 11-3, Figure 11-4, and Figure 11-5)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Setup Time for A[9:0] Valid to CS Active
t1
0
ns
Setup Time for CS Active to RD, WR, or DS
Active
t2
Delay Time from RD or DS Active to D[7:0]
Valid
t3
Hold Time from RD or WR or DS Inactive to
CS Inactive
t4
Hold Time from CS or RD or DS Inactive to
D[7:0] Tri-State
t5
Wait Time from WR or DS Active to Latch
D[7:0]
t6
D[7:0] Setup Time to WR or DS Inactive
t7
D[7:0] Hold Time from WR or DS Inactive
t8
A[9:0] Hold from WR or RD or DS Inactive
t9
0
ns
65
ns
0
ns
5.0
20
ns
65
ns
10
ns
2.0
ns
5.0
ns
RD, WR, or DS Inactive Time
t10
75
ns
Muxed Address Valid to ALE Falling
t11
(Note 10)
10
ns
Muxed Address Hold Time
t12
(Note 10)
10
ns
ALE Pulse Width
Setup Time for ALE High or Muxed
Address Valid to CS Active
SCLK Period
t13
(Note 10)
t14
(Note 10)
t15
30
ns
0
ns
19
31
ns
SCLK High and Low Time
SCLK Duty Cycle (High/Low)
t16
t16/t15
7.0
ns
40
60
%
Note 10: In nonmultiplexed bus applications (Figure 11-4), ALE should be connected high. In multiplexed bus applications (Figure 11-5), A[7:0]
are normally connected to D[7:0] externally, and the falling edge of ALE latches the address.
Note 11: Whenever CS = 0 and RD = 0 in Intel mode or CS = 0 and R/WR = 1 and DS = 0 in Motorola mode, the bidirectional data bus D[7:0] is
driven as an output.
Figure 11-3. SCLK Clock Timing
SCLK
t15
t16
HIGH
t16
LOW
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