DS1345Y Datasheet, PDF (8/12 Pages) Dallas Semiconductor – 1024k Nonvolatile SRAM with Battery Monitor

POWER-DOWN/POWER-UP TIMING
PARAMETER
SYMBOL
V_CC Fail Detect to CE and WE Inactive
t_PD
V_CC slew from V_TP to 0V
t_F
V_CC Fail Detect to RST Active
t_RPD
V_CC slew from 0V to V_TP
t_R
V_CC Valid to CE and WE Inactive
t_PU
V_CC Valid to End of Write Protection
t_REC
V_CC Valid to RST Inactive
t_RPU
V_CC Valid to BW Valid
t_BPU
MIN
150
150
150
TYP
200
DS1345Y/AB
(t_A: See Note 10)
MAX UNITS NOTES
1.5
µs
11
µs
15
µs
14
µs
2
ms
125
ms
350
ms
14
1
s
14
BATTERY WARNING TIMING
PARAMETER
Battery Test Cycle
Battery Test Pulse Width
Battery Test to BW Active
SYMBOL
t_BTC
t_BTPW
t_BW
MIN
TYP
24
(t_A: See Note 10)
MAX UNITS NOTES
hr
1
s
1
s
PARAMETER
Expected Data Retention Time
SYMBOL MIN TYP
t_DR
10
MAX
(t_A=25°C)
UNITS NOTES
years
9
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery
backup mode.
NOTES:
1. WE is high for a Read Cycle.
2. OE = V_IH or V_IL. If OE = V_IH during write cycle, the output buffers remain in a high-impedance state.
3. t_WP is specified as the logical AND of CE and WE . t_WP is measured from the latter of CE or WE
going low to the earlier of CE or WE going high.
4. t_DS is measured from the earlier of CE or WE going high.
5. These parameters are sampled with a 5 pF load and are not 100% tested.
6. If the CE low transition occurs simultaneously with or latter than the WE low transition, the output
buffers remain in a high-impedance state during this period.
7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output
buffers remain in high-impedance state during this period.
8. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition,
the output buffers remain in a high impedance state during this period.
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