DS89C430 Datasheet, PDF (7/48 Pages) Dallas Semiconductor – Ultra-High-Speed Flash Microcontrollers

DS89C430/DS89C440/DS89C450
Note 15:
The clock divide and crystal multiplier control bits in the PMR register determine the system clock frequency and the minimum/
maximum external clock speed. The term “1/tCLCL” used in the AC Characteristics variable timing table is determined from the
following table. The minimum/maximum external clock speed columns clarify that [(external clock speed) x (multipliers)] cannot
exceed the rated speed of the device. In addition, the use of the crystal multiplier feature establishes a minimum external speed.
4X/2X
1
0
X
X
X
CD1
0
0
0
1
1
CD0
0
0
1
0
1
Number of External Clock
Cycles per System Clock
(1/tCLCL)
1/4
1/2
Reserved
1
1024
External Clock Speed
Min
Max
5MHz
10MHz
—
See AC Characteristics
See AC Characteristics
8.25MHz
16.5MHz
—
See AC Characteristics
See AC Characteristics
Note 16: External MOVX instruction times are dependent upon the setting of the MD2, MD1, and MD0 bits in the clock control register. The
terms “tSTC1, tSTC2, tSTC3” used in the variable timing table above are calculated through the use of the table given below.
MD2
0
0
0
0
1
1
1
1
MD1
0
0
1
1
0
0
1
1
MD0
0
1
0
1
0
1
0
1
MOVX Instruction Time
2 Machine Cycles
3 Machine Cycles
4 Machine Cycles
5 Machine Cycles
6 Machine Cycles
7 Machine Cycles
8 Machine Cycles
9 Machine Cycles
tSTC1
0 tCLCL
2 tCLCL
6 tCLCL
10 tCLCL
14 tCLCL
18 tCLCL
22 tCLCL
26 tCLCL
tSTC2
0 tCLCL
1 tCLCL
1 tCLCL
1 tCLCL
5 tCLCL
5 tCLCL
5 tCLCL
5 tCLCL
tSTC3
0 tCLCL
0 tCLCL
0 tCLCL
0 tCLCL
4 tCLCL
4 tCLCL
4 tCLCL
4 tCLCL
tSTC4
0 tCLCL
0 tCLCL
0 tCLCL
0 tCLCL
1 tCLCL
1 tCLCL
1 tCLCL
1 tCLCL
tSTC5
0 tCLCL
1 tCLCL
1 tCLCL
1 tCLCL
1 tCLCL
1 tCLCL
1 tCLCL
1 tCLCL
Note 17: Maximum load capacitance (to meet the above timing) for Port 0, ALE, PSEN, WR, and RD is limited to 60pF. XTAL1 and XTAL2 load
capacitance are dependent upon the frequency of the selected crystal.
Figure 1. Nonpage Mode Timing
XTAL1
ALE
PSEN
RD
WR
Port 0
Port 2
tCLCL
tAVLL2
tAVLL
tLLPL
tPXIX
tLLIV
tLLAX
LSB
MOVX
tPXIZ
MSB
tLHLL
tAVLL3
tLLAX3
tLLAX2
tPLPH
tPLIV
tRLRH
tPLAZ
tAVDV0
tAVIV0
tRLDV
LSB
MOVX
LSB
tLLDV
tRHDX
tAVWL0
tRHDZ
DATA
LSB
OPCODE
tWHLH
tLLWL
tWLWH
tWHQX
tQVWX
LSB
DATA
tAVWL2
MSB
tAVDV2
MSB
tAVIV2
MSB
MSB
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