DS89C430 Datasheet, PDF (30/48 Pages) Dallas Semiconductor – Ultra-High-Speed Flash Microcontrollers

DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers
Figure 10. Page Mode 1, External Memory Cycle (CD1:CD0 = 10)
Internal Memory Cycles
XTAL1
ALE
PSEN
RD/WR
Port 0
External Memory Cycles
Inst Inst ^{MOVX MOVX}
Data
Inst
Data
PAGES=00
Port 2
ALE
MSB LSB LSB LSB LSB MSB LSB MSB LSB MSB LSB MSB
Page Miss
Page Hit
Data Access
MOVX executed
Page Miss Data Access
MOVX executed
PSEN
RD/WR
Port 0
Port 2
ALE
PSEN
RD/WR
Port 0
Port 2
MOVX
Inst
Data
PAGES=01
MSBAdd
LSB Add
Page Miss
LSB Add
MSBAdd
LSB Add
Page Hit
Data Access
MOVX executed
MSBAdd
Page Miss
next instruction
MSBAdd
Page Miss
Inst
LSB Add
Data
LSB Add
Data Access
PAGES=10
During a page miss, P2 drives the Addr [8:15] of the 16-bit address and holds it for the duration of the first half of
the memory cycle to allow the external address latches to latch the new most significant address byte. ALE is
asserted to strobe the external address latches. During this operation, PSEN, RD, and WR are held in inactive
states and P0 is in a high-impedance state. The following half-memory cycle is executed as a page hit cycle and
the appropriate operation takes place.
A page miss can occur at set intervals or during external operations that require a memory access into a page of
memory that has not been accessed during the last external cycle. Generally, the first external memory access
causes a page miss. The new page address is stored internally and is used to detect a page miss for the current
external memory cycle.
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