DS1486 Datasheet, PDF (7/17 Pages) Dallas Semiconductor – RAMified Watchdog Timekeeper

DS1486/DS1486P
TIME OF DAY ALARM MASK BITS Figure 3
REGISTER
(3) MINUTES (5) HOURS
(7) DAYS
1
1
1
ALARM ONCE PER MINUTE
0
1
1
ALARM WHEN MINUTES MATCH
0
0
1
ALARM WHEN HOURS AND MINUTES MATCH
0
0
0
ALARM WHEN HOURS, MINUTES, AND DAYS MATCH
NOTE: ANY OTHER BIT COMBINATIONS OF MASK BIT SETTINGS PRODUCE ILLOGICAL OPERATION.
COMMAND REGISTER
Address location 0Bh is the Command Register where mask bits, control bits and flag bits reside. The
operation of each bit is as follows:
TE - Bit 7 Transfer enable - This bit when set to a logic 0 will disable the transfer of data between
internal and external clock registers. The contents in the external clock registers are now frozen and reads
or writes will not be affected with updates. This bit must be set to a logic 1 to allow updates.
IPSW - Bit 6 Interrupt switch - When set to a logic 1, INTA is the Time of Day Alarm and INTB/( INTB )
is the Watchdog Alarm. When set to logic 0, this bit reverses the output pins. INTA is now the Watchdog
Alarm output and INTB/( INTB ) is the Time of Day Alarm output. The INTA /SQW output pin shares both
the interrupt A and square wave output function. INTA and the square wave function should never be
simultaneously enabled or a conflict may occur (32-pin DIP module only).
IBH/LO - Bit 5 Interrupt B Sink or Source Current - When this bit is set to a logic 1 and V_CC is applied,
INTB/( INTB ) will source current (see DC characteristics IOH). When this bit is set to a logic 0, INTB
will sink current (see DC characteristics IOL).
PU/LVL - Bit 4 Interrupt pulse mode or level mode - This bit determines whether both interrupts will
output a pulse or level signal. When set to a logic 0, INTA and INTB/( INTB ) will be in the level mode.
When this bit is set to a logic 1, the pulse mode is selected and INTA will sink current for a minimum of
3 ms and then release. INTB/( INTB ) will either sink or source current, depending on the condition of Bit
5, for a minimum of 3 ms and then release. INTB will only source current when there is a voltage present
on V_CC.
WAM - Bit 3 Watchdog Alarm Mask - When this bit is set to a logic 0, the Watchdog Interrupt output
will be activated. The activated state is determined by bits 1,4,5, and 6 of the COMMAND REGISTER.
When this bit is set to a logic 1, the Watchdog interrupt output is deactivated.
TDM - Bit 2 Time of Day Alarm Mask - When this bit is set to a logic 0, the Time of Day Alarm
Interrupt output will be activated. The activated state is determined by bits 0, 4, 5, and 6 of the
COMMAND REGISTER. When this bit is set to a logic 1, the Time of Day Alarm interrupt output is
deactivated.
WAF - Bit 1 Watchdog Alarm Flag - This bit is set to a logic 1 when a watchdog alarm interrupt occurs.
This bit is read only.
The bit is reset when any of the Watchdog Alarm registers are accessed.
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