DS1486 Datasheet, PDF (2/17 Pages) Dallas Semiconductor – RAMified Watchdog Timekeeper

DS1486/DS1486P
DESCRIPTION
The DS1486 is a nonvolatile Static RAM with a full function Real-time clock (RTC), alarm, watchdog
timer, and interval timer which are all accessible in a bytewide format. The DS1486 contains a lithium
energy source and a quartz crystal which eliminate the need for any external circuitry. Data contained
within 128K by 8-bit memory and the timekeeping registers can be read or written in the same manner as
bytewide static RAM. The timekeeping registers are located in the first 14 bytes of memory space. Data
is maintained in the RAMified Timekeeper by intelligent control circuitry which detects the status of V_CC
and write-protects memory when V_CC is out of tolerance. The lithium energy source can maintain data and
real time for over 10 years in the absence of V_CC. Timekeeper information includes hundredths of
seconds, seconds, minutes, hours, day, date, month, and year. The date at the end of the month is
automatically adjusted for months with less than 31 days, including correction for leap year. The
RAMified Timekeeper operates in either 24-hour or 12-hour format with an AM/PM indicator. The
watchdog timer provides alarm interrupts and interval timing between 0.01 seconds and 99.99 seconds.
The real time alarm provides for preset times of up to one week. Interrupts for both watchdog and RTC
will operate when system is powered down. Either can provide system “wake-up” signals.
PACKAGES
The DS1486 is available in two packages: 32-pin DIP module and 34-pin PowerCap module. The 32-pin
DIP style module integrates the crystal, lithium energy source, and silicon all in one package. The 32-pin
PowerCap Module Board is designed with contacts for connection to a separate PowerCap
(DS90934PCX) that contains the crystal and battery. The design allows the PowerCap to be mounted on
top of the DS1486P after the completion of the surface mount process. Mounting the PowerCap after the
surface mount process prevents damage to the crystal and battery due to high temperatures required for
solder reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap Module Board and
PowerCap are ordered separately and shipped in separate containers. The part number for the PowerCap
is DS9034PCX.
OPERATION - READ REGISTERS
The DS1486 executes a read cycle whenever WE (Write Enable) is inactive (High), CE (Chip Enable)
and OE (Output Enable) are active (Low). The unique address specified by the address inputs (A0-A16)
defines which of the registers is to be accessed. Valid data will be available to the eight data output
drivers within t_ACC (Access Time) after the last address input signal is stable, providing that CE and OE
access times are also satisfied. If OE and CE access times are not satisfied, then data access must be
measured from the latter occurring signal ( CE or OE ) and the limiting parameter is either t_CO for CE or
t_OE for OE rather than address access.
OPERATION - WRITE REGISTERS
The DS1486 is in the write mode whenever the WE (Write Enable) and CE (Chip Enable) signals are in
the active (Low) state after the address inputs are stable. The latter occurring falling edge of CE or WE
will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE
or WE . All address inputs must be kept valid throughout the write cycle. WE must return to the high state
for a minimum recovery state (t_WR) before another cycle can be initiated. Data must be valid on the data
bus with sufficient Data Set-Up (t_DS) and Data Hold Time (t_DH) with respect to the earlier rising edge of
CE or WE . The OE control signal should be kept inactive (High) during write cycles to avoid bus
contention. However, if the output bus has been enabled ( CE and OE active), then WE will disable the
outputs in t_ODW from its falling edge.
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