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| DS1350W Datasheet, PDF (7/11 Pages) Dallas Semiconductor – 3.3V 4096K Nonvolatile SRAM with Battery Monitor | |||
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DS1350W
POWERâDOWN/POWERâUP TIMING
PARAMETER
SYMBOL MIN
VCC Fail Detect to CE and WE
tPD
Inactive
VCC slew from VTP to 0V
VCC Fail Detect to RST Active
VCC slew from 0V to VTP
VCC Valid to CE and WE
Inactive
tF
150
tRPD
tR
150
tPU
VCC Valid to End of Write
Protection
tREC
VCC Valid to RST Inactive
VCC Valid to BW Valid
tRPU
150
tBPU
TYP
200
MAX
1.5
15
2
125
350
1
(tA: See Note 10)
UNITS NOTES
µs
11
µs
µs
14
µs
ms
ms
ms
14
s
14
BATTERY WARNING TIMING
(tA: See Note 10)
PARAMETER
SYMBOL MIN
TYP
MAX
UNITS NOTES
Battery Test Cycle
tBTC
24
hr
Battery Test Pulse Width
tBTPW
1
s
Battery Test to BW Active
tBW
1
s
PARAMETER
(tA = 25°C)
SYMBOL MIN
TYP
MAX
UNITS NOTES
Expected Data Retention Time
tDR
10
years
9
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery backup mode.
NOTES:
1. WE is high for a Read Cycle.
2. OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high impedance state.
3. tWP is specified as the logical AND of CE and WE. tWP is measured from the latter of CE or WE going low to the
earlier of CE or WE going high.
4. tDS is measured from the earlier of CE or WE going high.
5. These parameters are sampled with a 5 pF load and are not 100% tested.
6. If the CE low transition occurs simultaneously with or latter than the WE low transition, the output buffers remain
in a high impedance state during this period.
7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output buffers remain
in high impedance state during this period.
8. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition, the output buffers
remain in a high impedance state during this period.
022598 7/11
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