DS1609 Datasheet, PDF (6/7 Pages) Dallas Semiconductor – Dual Port RAM

DS1609
DUAL PORT RAM TIMING: READ CYCLE
DURING READ CYCLE WE = V_IH
AD0 – AD7
CE
OE
ADDRESS VALID
t_AS
t_AH
DON’T CARE
DATA OUT VALID
t_COE
t_OEA
t_CEZ
t_OEZ
NOTES:
1. During read cycle the address must be off the bus prior to t_OEA minimum to avoid bus contention.
2. Read cycles are terminated by the first occurring rising edge of OE or CE.
DUAL PORT RAM TIMING: WRITE CYCLE
DURING WRITE CYCLE OE = V_IH
AD0 – AD7
CE
ADDRESS VALID
t_AS
t_AH
DON’T CARE
DATA IN VALID
t_CWE
t_DS
t_DH
t_WP
WE
NOTE:
1. Write cycles are terminated by the first occurring edge of WE or CE.
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