DS1554 Datasheet, PDF (6/21 Pages) Dallas Semiconductor – 256K NV Y2KC Timekeeping RAM

DS1554 REGISTER MAP Table 2
DATA
ADDRESS
B₇
B₆
B₅
B₄
B₃
B₂
B₁ B₀
7FFFh
10 Year
YEAR
7FFEh
X
X
X
10 M
MONTH
7FFDh
X
X
10 Date
DATE
7FFCh
X
FT
X
X
X
DAY
7FFBh
X
X
10 HOUR
HOUR
7FFAh
X
10 MINUTES
MINUTES
7FF9h
OSC
10 SECONDS
SECONDS
7FF8h
W
R
10 CENTURY
CENTURY
7FF7h WDS BMB4 BMB3 BMB2 BMB1 BMB0 RB1 RB0
7FF6h
AE
Y
ABE
Y
Y
Y
YY
7FF5h AM4 Y
10 DATE
DATE
7FF4h AM3 Y
10 HOURS
HOURS
7FF3h AM2
10 MINUTES
MINUTES
7FF2h AM1
10 SECONDS
SECONDS
7FF1h
Y
Y
Y
Y
Y
Y
YY
7FF0h
WF AF
0
BLF
0
0
00
DS1554
FUNCTION/RANGE
YEAR
MONTH
DATE
DAY
HOUR
MINUTES
SECONDS
CONTROL
WATCHDOG
INTERRUPTS
ALARM DATE
ALARM HOURS
ALARM MINUTES
ALARM SECONDS
UNUSED
FLAGS
00-99
01-12
01-31
01-07
00-23
00-59
00-59
00-39
01-31
00-23
00-59
00-59
X = Unused, read/writable under Write and Read
bit control
FT = Frequency Test bit
OSC = Oscillator start/stop bit
W = Write bit
R = Read bit
WDS = Watchdog Steering bit
BMB0-BMB4 = Watchdog Multiplier bits
RB0-RB1 = Watchdog Resolution bits
AE = Alarm Flag Enable
Y = Unused, read/writable without Write and Read
bit control
ABE = Alarm in battery Back-up mode enable
AM1-AM4 = Alarm Mask bits
WF = Watchdog Flag
AF = Alarm Flag
0 = 0 and are read only
BLF = Battery Low Flag
CLOCK OSCILLATOR CONTROL
The Clock oscillator may be stopped at any time. To increase the shelf life of the backup lithium battery
source, the oscillator can be turned off to minimize current drain from the battery. The OSC bit is the
MSB of the Seconds Register (B7 of 7FF9h). Setting it to a 1 stops the oscillator, setting to a 0 starts the
oscillator. The DS1554 is shipped from Dallas Semiconductor with the clock oscillator turned off, OSC
bit set to a 1.
READING THE CLOCK
When reading the RTC data, it is recommended to halt updates to the external set of double-buffered RTC
Registers. This puts the external registers into a static state allowing data to be read without register
values changing during the read process. Normal updates to the internal registers continue while in this
state. External updates are halted when a 1 is written into the read bit, B6 of the Control Register (7FF8h).
As long as a 1 remains in the Control Register read bit, updating is halted. After a halt is issued, the
registers reflect the RTC count (day, date, and time) that was current at the moment the halt command
was issued. Normal updates to the external set of registers will resume within 1 second after the read bit is
set to a 0.
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