DS1236 Datasheet, PDF (6/19 Pages) Dallas Semiconductor – MicroManager Chip

DS1236
low at the time power-fail detection occurs, CEO is held in its present state until CEI is returned high, or
the period t_CE expires. This delay of write protection until the current memory cycle is completed prevents
the corruption of data. If CEO is in an inactive state at the time of V_CC fail detection, CEO will be
unconditionally disabled within t_CF. During nominal supply conditions CEO will follow CEI with a
maximum propagation delay of 20 ns. Figure 7 shows a typical nonvolatile SRAM application.
FRESHNESS SEAL
In order to conserve battery capacity during storage and/or shipment of an end system, the DS1236
provides a freshness seal to electrically disconnect the battery. Figure 8 depicts the three pulses below
ground on the IN pin required to invoke the freshness seal. The freshness seal will be disconnected and
normal operation will begin when V_CC is cycled and reapplied to a level above V_BAT.
To prevent negative pulses associated with noise from setting the freshness mode in system applications,
a series diode and resistor can be used to shunt noise to ground. During manufacturing, the freshness seal
can still be set by holding TP2 at -3 volts while applying the 0 to –3 volts clock to TP1.
POWER SWITCHING
When larger operating currents are required in a battery backed system, the 5-volt supply and battery
supply switches internal to the DS1236 may not be large enough to support the required load through
V_CCO with a reasonable voltage drop. For these applications, the PF and PF outputs are provided to gate
external power switching devices. As shown in Figure 9, power to the load is switched from V_CC to
battery on power-down, and from battery to V_CC on power-up. The DS1336 is designed to use the PF
output to switch between V_BAT and V_CC. It provides better leakage and switchover performance than
currently available discrete components. The transition threshold for PF and PF is set to the external
battery voltage V_BAT, allowing a smooth transition between sources. The load applied to the PF pin from
the external switch will be supplied by the battery. Therefore, if a discrete switch is used, this load should
be taken into consideration when sizing the battery.
RESET CONTROL
As mentioned above, the DS1236 supports two modes of operation. The CMOS mode is used when the
system incorporates a CMOS microprocessor which is battery backed. The NMOS mode is used when a
non-battery backed processor is incorporated. The mode is selected by the RC (Reset Control) pin. The
level of this pin distinguishes timing and level control on RST, RST , and NMI outputs for volatile
processor operation versus nonvolatile battery backup or battery operated processor applications.
ST/INPUT TIMING Figure 2
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