DS1236 Datasheet, PDF (5/19 Pages) Dallas Semiconductor – MicroManager Chip

DS1236 FUNCTIONAL BLOCK DIAGRAM Figure 1
DS1236
If the IN pin is connected to V_CCO, the NMI output will pulse low as V_CC decays to V_CCTP in the NMOS
mode (RC=0). In the CMOS mode (RC=V_CCO) the power-down of V_CC out-of-tolerance at V_CCTP will not
produce a pulse on the NMI pin. Given that any NMI pulse has been completed by the time V_CC decays
to V_CCTP, the NMI pin will remain high. The NMI voltage will follow V_CC down until V_CC decays to
V_BAT. Once V_CC decays to V_BAT, the NMI pin will either remain at V_OHL or enter tri-state mode as
determined by the RC pin (see “Reset Control” section).
MEMORY BACKUP
The DS1236 provides all of the necessary functions required to battery back a static RAM. First, a switch
is provided to direct SRAM power from the incoming 5-volt supply (V_CC) or from an external battery
(V_BAT), whichever is greater. This switched supply (V_CCO) can also be used to battery back a CMOS
microprocessor. For more information about nonvolatile processor applications, review the “Reset
Control” and “Wake Control” sections. Second, the same power-fail detection described in the power
monitor section is used to hold the chip enable output ( CEO ) to within 0.3 volts of V_CC or to within 0.7
volts of V_BAT. This write protection mechanism occurs as V_CC falls below V_CCTP as specified. If CEI is
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