DS1220Y Datasheet, PDF (6/8 Pages) Dallas Semiconductor – 16k Nonvolatile SRAM

POWER-DOWN/POWER-UP CONDITION
DS1220Y
SEE NOTE 11
POWER-DOWN/POWER-UP TIMING
PARAMETER
SYMBOL
CE at V_IH before Power-Down
t_PD
V_CC Slew from V_TP to 0V
t_F
V_CC Slew from 0V to V_TP
t_R
CE at V_IH after Power-Up
t_REC
PARAMETER
Expected Data Retention Time
SYMBOL
t_DR
MIN
0
100
0
MIN
10
MAX
2
MAX
UNITS
µs
µs
µs
ms
UNITS
years
NOTES
11
(T_A = 25°C)
NOTES
9
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery
backup mode.
NOTES:
1. WE is high for a read cycle.
2. OE = V_IH or V_IL . If OE = V_IH during a write cycle, the output buffers remain in a high impedance
state.
3. t_WP is specified as the logical AND of CE and WE . t_WP is measured from the latter of CE or WE
going low to the earlier of CE or WE going high.
4. t_DS are measured from the earlier of CE or WE going high.
5. These parameters are sampled with a 5 pF load and are not 100% tested.
6. If the CE low transition occurs simultaneously with or later than the WE low transition in write
cycle 1, the output buffers remain in a high impedance state during this period.
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