DS1747 Datasheet, PDF (5/18 Pages) Dallas Semiconductor – Y2K-Compliant, Nonvolatile Timekeeping RAMs

DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs
Table 2. Register Map
ADDRESS
B7
7FFFF
7FFFE
X
7FFFD
X
DATA
B6
B5
B4
B3
10 Year
X
X
10 Month
X
10 Date
7FFFC
BF
FT
X
X
X
7FFFB
X
X
10 Hour
7FFFA
7FFF9
X
OSC
10 Minutes
10 Seconds
7FFF8
W
R
10 Century
B2
B1
Year
Month
Date
Day
Hour
Minutes
Seconds
Century
B0
FUNCTION RANGE
Year
00-99
Month
01-12
Date
01-31
Day
01-07
Hour
Minutes
00-23
00-59
Seconds 00-59
Century 00-39
OSC = Stop Bit
R = Read Bit
FT = Frequency Test
W = Write Bit
X = See Note
BF = Battery Flag
NOTE: All indicated “X” bits are not dedicated to any particular function and can be used as normal RAM bits.
RETRIEVING DATA FROM RAM OR CLOCK
The DS1747 is in the read mode whenever OE (output enable) is low, WE (write enable) is high, and CE
(chip enable) is low. The device architecture allows ripple-through access to any of the address locations
in the NV SRAM. Valid data will be available at the DQ pins within tAA after the last address input is
stable, providing that the CE and OE access times and states are satisfied. If CE or OE access times and
states are not met, valid data will be available at the latter of chip-enable access (t_CEA) or at output enable
access time (t_OEA). The state of the data input/output pins (DQ) is controlled by CE and OE. If the
outputs are activated before t_AA, the data lines are driven to an intermediate state until tAA. If the address
inputs are changed while CE and OE remain valid, output data will remain valid for output data hold
time (t_OH) but will then go indeterminate until the next address access.
WRITING DATA TO RAM OR CLOCK
The DS1747 is in the write mode whenever WE, and CE are in their active state. The start of a write is
referenced to the latter occurring transition of WE or CE. The addresses must be held valid throughout
the cycle. CE or WE must return inactive for a minimum of tWR prior to the initiation of another read or
write cycle. Data in must be valid t_DS prior to the end of write and remain valid for tDH afterward. In a
typical application, the OE signal will be high during a write cycle. However, OE can be active provided
that care is taken with the data bus to avoid bus contention. If OE is low prior to WE transitioning low
the data bus can become active with read data defined by the address inputs. A low transition on WE
will then disable the output t_WEZ after WE goes active.
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