DS1007 Datasheet, PDF (5/6 Pages) Dallas Semiconductor – 7-1 Silicon Delay Line

NOTES:
1. All voltages are referenced to ground.
DS1007
2. Measured with outputs open.
3. V_CC = 5V @25°C. Delays accurate on rising edges within ±2 ns.
4. See Test Conditions below.
5. All output delays in the same speed output tend to vary unidirectionally with temperature or voltage
range (i.e., if Out 2 slows down, all other outputs also slow down).
6. Period specifications may be exceeded; however, accuracy will be application-sensitive (decoupling,
layout, etc.).
7. t_PU = 0 ms for Out 1 through Out 4.
TERMINOLOGY
Period: The time elapsed between the leading edge of the first pulse and the leading edge of the
following pulse.
t_WI (Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge and the
1.5V point on the trailing edge, or the 1.5V point on the trailing edge and the 1.5V point on the leading
edge.
t_RISE (Input Rise Time): The elapsed time between the 20% and the 80% point on the leading edge of the
input pulse.
t_FALL (Input Fall Time): The elapsed time between the 80% and the 20% point on the trailing edge of the
input pulse.
t_PLH (Time Delay, Rising): The elapsed time between the 1.5V point on the leading edge of the input
pulse and the 1.5V point on the leading edge of the corresponding output pulse.
TEST SETUP DESCRIPTION
Figure 3 illustrates the hardware configuration used for measuring the timing parameters on the DS1007.
The input waveform is produced by a precision pulse generator under software control. Time delays are
measured by a time interval counter (20 ps resolution) connected between the input and each output. Each
output is selected and connected to the counter by a VHF switch control unit. All measurements are fully
automated, with each instrument controlled by a central computer over an IEEE 488 bus.
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