DS1267 Datasheet, PDF (4/12 Pages) Dallas Semiconductor – Dual Digital Potentiometer Chip

DS1267
STACKED CONFIGURATION
The potentiometers of the DS1267 can be connected in series as shown in Figure 3. This is referred to as
the stacked configuration. The stacked configuration allows the user to double the total end-to-end
resistance of the part and the number of steps to 512 (or 9 bits of resolution).
The wiper output for the combined stacked potentiometer will be taken at the S_OUT pin, which is the
multiplexed output of the wiper of potentiometer-0 (W0) or potentiometer-1 (W1). The potentiometer
wiper selected at the S_OUT output is governed by the setting of the stack select bit (bit 0) of the 17-bit I/O
shift register. If the stack select bit has value 0, the multiplexed output, S_OUT, will be that of the
potentiometer-0 wiper. If the stack select bit has value 1, the multiplexed output, S_OUT, will be that of the
potentiometer-1 wiper.
STACKED CONFIGURATION Figure 3
CASCADE OPERATION
A feature of the DS1267 is the ability to control multiple devices from a single processor. Multiple
DS1267s can be linked or daisy-chained as shown in Figure 4. As a data bit is entered into the I/O shift
register of the DS1267 a bit will appear at the C_OUT output within a maximum delay of 50 nanoseconds.
The stack select bit of the DS1267 will always be the first out the part at the beginning of a transaction.
Additionally the C_OUT pin is always active regardless of the state of RST . This allows one to read the I/O
shift register without changing its value.
CASCADING MULTIPLE DEVICES Figure 4
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