DS1267 Datasheet, PDF (10/12 Pages) Dallas Semiconductor – Dual Digital Potentiometer Chip

DS1267
4. Relative linearity is used to determine the change in voltage between successive tap positions. Device
test limits ±0.5 LSB.
5. Typical values are for T_A = 25°C and nominal supply voltage.
6. -3 dB cutoff frequency characteristics for the DS1267 depend on potentiometer total resistance:
DS1267-010: 1 MHz; DS1267-050: 200 kHz; DS1267-100: 100 kHz.
7. C_OUT is active regardless of the state of RST .
8. See Figure 9(a), (b), and (c).
9. See Figure 11.
10. Valid at 25°C only.
TIMING DIAGRAMS Figure 9
(A) 3-WIRE SERIAL INTERFACE GENERAL OVERVIEW
(B) START OF COMMUNICATION TRANSACTION
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