DS21352 Datasheet, PDF (38/137 Pages) Dallas Semiconductor – 3.3V DS21352 and 5V DS21552 T1 Single-Chip Transceivers

DS21352/DS21552
6.5 PULSE DENSITY ENFORCER
The Framer always examines both the transmit and receive data streams for violations of the following rules which are
required by ANSI T1.403:
– no more than 15 consecutive zeros
– at least N ones in each and every time window of 8 x (N +1) bits where N = 1 through 23
Violations for the transmit and receive data streams are reported in the RIR2.0 and RIR2.1 bits
respectively. When the CCR3.3 is set to one, the DS21352 will force the transmitted stream to meet this
requirement no matter the content of the transmitted stream. When running B8ZS, the CCR3.3 bit should
be set to zero since B8ZS encoded data streams cannot violate the pulse density requirements.
38 of 137