DS21352 Datasheet, PDF (135/137 Pages) Dallas Semiconductor – 3.3V DS21352 and 5V DS21552 T1 Single-Chip Transceivers

Figure 24-11 TRANSMIT SIDE TIMING
DS21352/DS21552
tR
TCLK
TESO
TSER / TSIG /
TDATA
TCHCLK
tF
t _D1
t _D2
tCP
tCL tCH
t _SU
tHD
TCHBLK
TSYNC1
TSYNC2
TLCLK5
tD2
t _SU
t _D2
t _D2
t _HD
tHD
TLINK
t _SU
Notes:
1. TSYNC is in the output mode (TCR2.2 = 1).
2. TSYNC is in the input mode (TCR2.2 = 0).
3. TSER is sampled on the falling edge of TCLK when the transmit side elastic store is disabled.
4. TCHCLK and TCHBLK are synchronous with TCLK when the transmit side elastic store is disabled.
5. TLINK is only sampled during F-bit locations.
6. No relationship between TCHCLK and TCHBLK and the other signals is implied.
135 of 137