DS87C530_05 Datasheet, PDF(34/47 Page) Dallas Semiconductor – EPROM/ROM Microcontrollers with Real-Time Clock

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DS87C530_05 Datasheet, PDF (34/47 Pages) Dallas Semiconductor – EPROM/ROM Microcontrollers with Real-Time Clock

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DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock

DC ELECTRICAL CHARACTERISTICS (continued)

(VCC = 4.5V to 5.5V, TA = -40Â°C to +85Â°C.)

PARAMETER

SYMBOL

MIN

Input Leakage Port 0, EA, Pins, I/O Mode

-10

Input Leakage Port 0, Bus Mode

-300

RST Pulldown Resistance

RRST

TYP

MAX

+10

+300

200

UNITS

NOTES

Note 1:

Note 2:

Note 3:

Note 4:

Note 5:

Note 6:

Note 7:

Note 8:

Note 9:

Note 10:

Note 11:

Note 12:

Note 13:

Note 14:

Storage temperature is defined as the temperature of the device when VCC = 0V and VBAT = 0V. In this state, the contents of

SRAM are not battery backed and are undefined.

All parameters apply to both commercial and industrial temperature operation unless otherwise noted.

All voltages are referenced to ground.

Active current measured with 33MHz clock source on XTAL1, VCC = RST = 5.5V, other pins disconnected.

Idle mode current measured with 33MHz clock source on XTAL1, VCC = 5.5V, RST at ground, other pins disconnected.

Stop mode current measured with XTAL1 and RST grounded, VCC = 5.5V, all other pins disconnected.

VCC = 0V, VBAT = 3.3V. 32.768kHz crystal with 12.5pF load capacitance between RTCX1 and RTCX2 pins. RTCE bit set to 1.

RST = VCC. This condition mimics operation of pins in I/O mode. Port 0 is tri-stated in reset and when at a logic high state during

I/O mode.

During a 0-to-1 transition, a one-shot drives the ports hard for two clock cycles. This measurement reflects port in transition

mode.

When addressing external memory. This specification only applies to the first clock cycle following the transition.

This is the current required from an external circuit to hold a logic low level on an I/O pin while the corresponding port latch bit is

set to 1. This is only the current required to hold the low level; transitions from 1 to 0 on an I/O pin will also have to overcome the

transition current.

Ports 1, 2, and 3 source transition current when being pulled down externally. It reaches its maximum at approximately 2V.

0.45 < VIN < VCC. RST = VCC. This condition mimics operation of pins in I/O mode.

0.45 < VIN < VCC. Not a high-impedance input. This port is a weak address holding latch in Bus Mode. Peak current occurs near

the input transition point of the latch, approximately 2V.

TYPICAL ICC vs. FREQUENCY

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