DS1603 Datasheet, PDF (3/8 Pages) National Semiconductor (TI) – TRI-STATE Dual Receiver

DS1603
DATA INPUT
Following the 8–bit protocol that inputs write mode, 32 bits of data are written to the selected counter on
the rising edge of the next 32 CLK cycles. After 32 bits have been entered any additional CLK cycles will
be ignored until RST is transitioned low to end data transfer and then high again to begin new data
transfer.
DATA OUTPUT
Following the eight CLK cycles that input read mode protocol, 32 bits of data will be output from the
selected counter on the next 32 CLK cycles. The first data bit to be transmitted from the selected 32–bit
counter occurs on the falling edge after the last bit of protocol is written. When transmitting data from
the selected 32–bit counter, RST must remain at high level as a transition to low level will terminate data
transfer. Data is driven out the DQ pin as long as CLK is low. When CLK is high the DQ pin is tristated.
OSCILLATOR OUTPUT
Pin 6 of the DS1603 module is a 1 Hz output signal. This signal is present only when V_CC is applied and
greater than the internal power supply. However, the output is guaranteed to meet TTL requirement only
while V_CC is within normal limits. This output can be used as a 1-second interrupt or time tick needed in
some applications.
INTERNAL POWER
The internal battery of the DS1603 module provides 35 mAh and will run the elapsed time counter for
over 10 years in the absence of power.
DS1603 ELAPSED TIME COUNTER BLOCK DIAGRAM Figure 1
PROTOCOL BIT MAP Figure 2
7
6
5
4
3
2
1
0
ACC
AVC
OSC2
OSC1
OSC0
CCC
CVC
RD
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