DS89C430_07 Datasheet, PDF (24/46 Pages) Dallas Semiconductor – Ultra-High-Speed Flash Microcontrollers

DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers
Table 4. In-Application Programming Commands
FC3:FC0
0000
0001
0010
0011
0100
1000
1001
1010
1011
1100
1101
1110
1111
COMMAND
Read Mode
Verify Option Control Register
Verify Security Block
Verify Upper Program
Memory Bank
Reserved for Future Use
Reserved for Future Use
Write Option Control Register
Write Security Block
Write Upper Program
Memory Bank
Erase Option Control Register
Erase Security Block
Erase Upper Program
Memory Bank
System Reset
OPERATION
Default state. All flash blocks are in read mode. Note: The upper bank
of flash memory is inaccessible for execution unless the FC3:0 bits are
in the read mode (0000b) state.
Read data from the option control register. Data is available in the
FDATA at the end of the following machine cycle. FDATA.3 is the logic
value of the watchdog POR default setting.
Read a byte of data from the security block. After the address byte is
written to the FDATA, data is available in the FDATA at the end of the
following machine cycle. (Lock bits are addressed at 40h and
FDATA.5:3 are the logic value of LB1, LB2 and LB3, respectively.)
Read a byte of data from upper flash memory bank (address range
from 2000h to 3FFFh). The first and second byte writes to the FDATA
are the upper and lower byte of the address. Data is available in the
FDATA at the end of the following machine cycle after the second
address byte is written.
This command should not be modified by user programs.
This command should not be modified by user programs.
Write to the option control register as data is written to FDATA. Bit 3 of
the data byte represents the watchdog POR default setting.
Write a byte of data to the security block at a selected locations
addressed by the first byte write to the FDATA. The second write to the
FDATA is the data byte. (Lock bits are addressed at 40h and the
FDATA 5:3 represents lock bits LB3, LB2, and LB1, respectively.)
Write a byte of code to the upper flash memory bank (address range
from 2000h to 3FFFh). The first and second byte writes to the FDATA
are the upper byte and the lower byte of the address. The third write to
the FDATA is the data byte.
Erase the option control register. The contents of this register are
returned to FFh. This operation disables the watchdog reset function on
power-up.
Erase the security flash block that contains the 64-byte encryption array
and the lock bits. The content of every memory location is turned into
FFh.
Erase the upper bank of flash memory bank. The contents of every
memory location are returned to FFh.
This command is used to cause a system reset.
The flash command bits are cleared to 0 on all forms of reset, and it is important for the user software to clear
these bits to 0 to return the flash memory to read mode from erase/program operation. This setting is a “no
operation” condition for the MMU, which allows the processor to return to its normal execution. Note that the busy
and error flags have no function in normal flash-read mode.
The FCNTL SFR can only be written using timed access. This procedure provides protection against inadvertent
erase/program operation on the flash memory. Any command written to the FCNTL during a flash operation is
ignored (FBUSY = 0). To ensure data integrity, an erase command sequence should be reinitiated if an erase or
program operation is interrupted by a reset.
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