DS17285 Datasheet, PDF (21/38 Pages) Dallas Semiconductor – 3V/5V Real-Time Clock

DS17285/DS17287
EXTENDED CONTROL REGISTERS
Two extended control registers are provided to supply controls and status information for the extended
features offered by the DS17285/DS17287. These are designated as extended control registers 4A and 4B
and are located in register bank 1, locations 04AH and 04BH, respectively. The functions of the bits
within these registers are described as follows.
EXTENDED CONTROL REGISTER 4A
MSB
BIT 7
VRT2
BIT 6
INCR
BIT 5
BME
BIT 4
*
BIT 3
PAB
BIT 2
RF
BIT 1
WF
LSB
BIT 0
KF
VRT2 – Valid RAM and Time 2. This status bit gives the condition of the auxiliary batter. It is set to a
logic 1 condition when the external lithium battery is connected to the V_BAUX. If this bit is read as a logivc
0, the external battery should be replaced.
INCR – Increment in Progress Status. This bit is set to a 1 when an increment to the time/date registers
is in progress and the alarm checks are being made. INCR is set to a 1 at 122µs before the update cycle
starts and is cleared to 0 at the end of each update cycle.
BME – Burst Mode Enable. The burst mode enable bit allows the extended user RAM address registers
to automatically increment for consecutive reads and writes. When BME is set to a logic 1, the automatic
incrementing is enabled and when BME is set to a logic 0, the automatic incrementing is disabled.
PAB – Power-Active Bar-Control. When this bit is 0, the PWR pin is in the active low state. When this
bit is 1, the PWR pin is in the high-impedance state. This bit can be written to a logic 1 or 0 by the user. If
either WF and WIE = 1 or KF and KSE = 1, the PAB bit is cleared to 0.
RF – Ram Clear Flag. This bit is set to a logic 1 when a high-to-low transition occurs on the RCLR
input if RCE = 1. The RF bit is cleared by writing it to a logic 0. This bit can also be written to a logic 1
to force an interrupt condition.
WF – Wake-Up Alarm Flag. This bit is set to 1 when a wake-up alarm condition occurs or when the
user writes it to a 1. WF is cleared by writing it to a 0.
KF – Kickstart Flag. This bit is set to a 1 when a kickstart condition occurs or when the user writes it to
a 1. This bit is cleared by writing it to a logic 0.
*Reserved bits. These bits are reserved for future use by Dallas Semiconductor. They can be read and
written, but have no affect on operation.
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